nb4l339 ON Semiconductor, nb4l339 Datasheet - Page 3

• Manufacturer Part Number: nb4l339
• Description: 3.3v 1 4 Clock Fanout Buffer
• Manufacturer: ON Semiconductor

1. In the differential configuration when the input termination pin (VTx / VTx) are connected to a common termination voltage or left open, and
Table 4. Pin Description
1, 8, EP
25, 32
9, 16,
Pin
if no signal is applied on CLKx / CLKx input then the device will be susceptible to self−oscillation.
10
12
13
14
15
17
18
19
20
21
22
23
24
26
27
28
29
30
31
11
2
3
4
5
6
7
−
CLKSEL
DIVSEL
Name
CLKA
CLKA
CLKB
CLKB
QD1
QD1
QD0
QD0
QC1
QC1
QC0
QC0
VTA
VTB
QB1
QB1
QB0
QB0
QA1
QA1
QA0
QA0
V
V
MR
EN
EP
EE
CC
LVCMOS/LVTTL
LVCMOS/LVTTL
LVCMOS/LVTTL
LVCMOS/LVTTL
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL, CML,
LVPECL, CML,
LVPECL, CML,
LVPECL, CML,
LVDS Input
LVDS Input
LVDS Input
LVDS Input
I/O
−
−
−
−
−
Synchronous Output Enable/Disable pin. This pin defaults LOW when left open with 80 kW
resistor to V
Master Reset Asynchronous. This pin defaults HIGH when left open with 80 kW resistor to
V
Negative Supply Voltage
Non−inverted differential input (A). (Note 1)
Internal 100−W center−tapped termination pin for CLKA and CLKA (Note 1).
Inverted differential input (A). (Note 1)
Non−inverted differential input (B). (Note 1)
Internal 100−W center−tapped termination pin for CLKB and CLKB. (Note 1)
Inverted differential input (B). (Note 1)
Positive Supply Voltage
Asynchronous Clock input select pin. This pin defaults LOW when left open with 80 kW
resistor to V
Inverted differential (D1) output. Typically terminated with 50 W resistor to V
Non−inverted Differential (D1) Output. Typically terminated with 50 W resistor to V
Inverted differential (D0) output. Typically terminated with 50 W resistor to V
Non−inverted Differential (D0) Output. Typically terminated with 50 W resistor to V
Inverted differential (C1) output. Typically terminated with 50 W resistor to V
Non−inverted Differential (C1) Output. Typically terminated with 50 W resistor to V
Inverted differential (C0) output. Typically terminated with 50 W resistor to V
Non−inverted Differential (C0) Output. Typically terminated with 50 W resistor to V
Inverted differential (B1) output. Typically terminated with 50 W resistor to V
Non−inverted Differential (B1) Output. Typically terminated with 50 W resistor to V
Inverted differential (B0) output. Typically terminated with 50 W resistor to V
Non−inverted Differential (B0) Output. Typically terminated with 50 W resistor to V
Inverted differential (A1) output. Typically terminated with 50 W resistor to V
Non−inverted Differential (A1) Output. Typically terminated with 50 W resistor to V
Inverted differential (A0) output. Typically terminated with 50 W resistor to V
Non−inverted Differential (A0) Output. Typically terminated with 50 W resistor to V
Asynchronous Divide Select Pin selects A divide block outputs to divide by 1 or divide by 2.
Defaults LOW when left open, divide−by−1, with 80 kW resistor to V
Exposed Pad. The exposed pad (EP) on package bottom (see case drawing) is thermally
connected to the die for improved heat transfer out of package and must be attached to a
heat−sinking conduit. The pad is electrically connected to V
V
CC
EE
.
on the PC board.
http://onsemi.com
EE
EE
.
.
3
Description
EE
and must be connected to
EE
.
CC
CC
CC
CC
CC
CC
CC
CC
– 2 V.
– 2 V.
– 2 V.
– 2 V.
– 2 V
– 2 V.
– 2 V.
– 2 V.
CC
CC
CC
CC
CC
CC
CC
CC
– 2 V.
– 2 V.
– 2 V.
– 2 V.
– 2 V.
– 2 V.
– 2 V.
– 2 V.