nb7l585 ON Semiconductor, nb7l585 Datasheet - Page 5

• Manufacturer Part Number: nb7l585
• Description: 2.5v / 3.3v Differential 2 1 Mux Input To 1 6 Lvpecl Clock/data Fanout Buffer / Translator
• Manufacturer: ON Semiconductor

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
11. Measured using a 400 mV pk−pk source, 50% duty cycle clock source. All output loading with external 50 W to V
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Input voltage swing is a single−ended measurement operating in differential mode.
17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
Table 6. AC CHARACTERISTICS
f
f
f
V
t
t
t
tskew
t
F
t
t
V
t
Symbol
MAX
DATAMAX
SEL
PLH
PHL
PLH
DC
JITTER
r,
OUTpp
FN
INPP
, t
N
rates 40 ps (20% − 80%).
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
inputs.
Figure 3. Clock Output Voltage Amplitude (V
f
,
TC
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Maximum Input Clock Frequency; V
Maximum Operating Data Rate (PRBS23)
Maximum Toggle Frequency, SEL
Output Voltage Amplitude (@ V
(Note 12) (Figures 8 and 10)
Propagation Delay to Differential Outputs, @ 1 GHz,
measured at differential crosspoint
Propagation Delay Temperature Coefficient
Output − Output skew (within device) (Note 13)
Device − Device skew (tpd max – tpdmin)
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
Phase Noise, f
Integrated Phase Jitter (Figure x) fin = 1 GHz, 12 kHz * 20 MHz Offset (RMS)
RJ – Output Random Jitter (Note 14)
DJ − Residual Output Deterministic Jitter (Note 15)
Crosstalk Induced Jitter (Adjacent Channel) (Note 17)
Input Voltage Swing (Differential Configuration) (Note 16)
Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q
in
= 1 GHz
1000
800
600
400
200
0
V
0
CC
INPPmin
Q AMP (mV)
= 2.375 V to 3.6 V; GND = 0 V; T
Characteristic
1
f
OUTpp
in
, CLOCK INPUT FREQUENCY (GHz)
)
2
w 400 mV
OUTpp
http://onsemi.com
3
) vs. Input Frequency (f
5
4
5
A
f
in
f
in
= −40°C to 85°C (Note 11)
v 5.0 GHz
f
f
in
in
≤ 5.0 GHz
IN/IN to Q/Q
≤ 8 Gbps
≤ 4 GHz
≤ 5 GHz
100 kHz
6
10 MHz
20 MHz
40 MHz
10 kHz
SEL to Q
1 MHz
7
in
) at Ambient Temperature (Typical)
8
Min
550
400
100
1.0
45
25
5
8
−135
−137
−149
−150
−150
−151
Typ
800
650
175
200
1.5
0.2
10
50
50
36
55
7
5
CC
1200
Max
– 2 V. Input edge
250
300
100
0.8
0.7
20
55
15
85
ps pk−pk
psRMS
Dfs/°C
ps rms
Gbps
Unit
GHz
GHz
dBc
mV
mV
ps
ps
ps
%
fs