nb100lvep222 ON Semiconductor, nb100lvep222 Datasheet

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nb100lvep222

Manufacturer Part Number
nb100lvep222
Description
2.5 V/3.3 V 1 15 Differential Ecl/pecl ??1/??2 Clock Driver
Manufacturer
ON Semiconductor
Datasheet

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NB100LVEP222
2.5 V/3.3 V 1:15 Differential
ECL/PECL ÷1/÷2 Clock Driver
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be used in a differential
configuration or single-ended (with V
and connected to the unused input of a pair). Either of two fully
differential clock inputs may be selected. Each of the four output
banks of 2, 3, 4, and 6 differential pairs may be independently
configured to fanout 1X or 1/2X of the input frequency. When the
output banks are configured with the B1 mode, data can also be
distributed. The LVEP222 specifically guarantees low output to output
skew. Optimal design, layout, and processing minimize skew within a
device and from lot to lot. This device is an improved version of the
MC100LVE222 with higher speed capability and reduced skew.
Any changes may cause indeterminate output states requiring an MR
pulse to resynchronize any 1/2X outputs (See Figure 4). Unused
output pairs should be left unterminated (open) to reduce power and
switching noise.
from a positive V
LVEP222 to be used for high performance clock distribution in
+2.5/3.3 V systems. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power
supplies. For more information on using PECL, designers should refer
to Application Note AN1406/D. For a SPICE model, refer to
Application Note AN1560/D.
this device only. For single- ended LVPECL input conditions, the
unused differential input is connected to V
voltage. V
V
or sinking to 0.5 mA. When not used, V
Single- ended CLK input operation is limited to a V
LVPECL mode, or V
Features
*For additional information on our Pb-Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2007
June, 2007- Rev. 10
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
BB
The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL
The fsel pins and CLK_Sel pin are asynchronous control inputs.
The NB100LVEP222, as with most ECL devices, can be operated
The V
V
NECL Mode Operating Range:
V
20 ps Output-to-Output Skew
85 ps Part-to-Part Skew
Selectable 1x or 1/2x Frequency Outputs
LVPECL Mode Operating Range:
Internal Input Pulldown Resistors
Performance Upgrade to ON Semiconductor's MC100LVE222
V
Pb-Free Packages are Available*
CC
CC
BB
and V
/V
/V
Output
BB
CC0
CC0
BB
CC
pin, an internally generated voltage supply, is available to
may also rebias AC coupled inputs. When used, decouple
/V
= 0 V with V
= 2.375 V to 3.8 V with V
CC0
CC
/V
via a 0.01 mF capacitor and limit current sourcing
EE
CC0
v -3.0 V in NECL mode.
EE
supply in LVPECL mode. This allows the
= -2.375 V to -3.8 V
BB
EE
BB
output reference bypassed
= 0 V
BB
as a switching reference
should be left open.
CC
/V
CC0
≥ 3.0 V in
1
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
*For additional marking information, refer to
Application Note AND8002/D.
CASE 485M
CASE 848H
MN SUFFIX
FA SUFFIX
LQFP-52
QFN-52
A
WL
YY
WW
G
ORDERING INFORMATION
1
52
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
Publication Order Number:
1
1
NB100LVEP222/D
52
DIAGRAMS*
52
AWLYYWWG
MARKING
AWLYYWWG
LVEP222
LVEP222
NB100
NB100

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nb100lvep222 Summary of contents

Page 1

... Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 4). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive V /V supply in LVPECL mode. This allows the ...

Page 2

... The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a CC0 heat-sinking conduit. This exposed pad is electrically connected to V NB100LVEP222 NB100LVEP222 internally. EE Figure 1. 52-Lead LQFP Pinout (Top View) http://onsemi ...

Page 3

... Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to V internally. EE NB100LVEP222 NB100LVEP222 Figure 2. QFN-52 Pinout (Top View CC0 http://onsemi.com 3 Exposed Pad (EP) ...

Page 4

... MR CLK0 CLK0 CLK1 CLK1 CLK_SEL V BB fsela fselb CC0 fselc V EE fseld CLK MR Q (B2) Q (B1) NB100LVEP222 ÷1 ÷2 Figure 3. Logic Diagram Figure 4. Master Reset (MR) Timing Diagram http://onsemi.com 4 Qa0:1 2 Qa0:1 3 Qb0:2 Qb0:2 Qc0:3 4 Qc0:3 Qd0:5 6 Qd0:5 ...

Page 5

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NB100LVEP222 Characteristics Human Body Model Machine Model ...

Page 6

... Input and output parameters vary 1:1 with V 7. All loading with -2 CC0 8. Single-Ended input operation is limited min varies 1:1 with IHCMR EE IHCMR differential input signal. NB100LVEP222 2 (Note 2) CC CC0 EE -40 °C Min Typ Max Min 100 ...

Page 7

... Input and output parameters vary 1:1 with V 11. All loading with 2 CC0 12. Single-Ended input operation is limited V 13. V min varies 1:1 with IHCMR EE IHCMR differential input signal. NB100LVEP222 0 -3 -2.375 V (Note 10) CC CC0 EE -40 °C Min Typ Max Min 100 ...

Page 8

... Measured with LVPECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 15. Skew is measured between outputs under identical transitions and operating conditions. 16. Device-to-Device skew for identical transitions at identical V 17 the differential configuration input voltage swing required to maintain AC characteristics including t PP NB100LVEP222 = V = 2.375 CC0 EE -40 ° ...

Page 9

... RMS JITTER 300 200 0.1 0.5 Figure 5. Output Voltage (V ) versus Input Frequency and Random Clock Jitter (t OPP V PP Figure 6. LVPECL Differential Input Levels NB100LVEP222 Q AMP (÷ AMP (÷ 1) 1.0 1.5 INPUT FREQUENCY (GHz (LVPECL) CC CC0 V (DIFF IHCMR ...

Page 10

... NB100LVEP222. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit ...

Page 11

... AND8002/D - AND8020/D - AND8066/D - AND8090/D - ORDERING INFORMATION Device NB100LVEP222FA NB100LVEP222FAG NB100LVEP222FAR2 NB100LVEP222FARG NB100LVEP222MNG NB100LVEP222MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB100LVEP222 = ...

Page 12

... SEATING PLANE 0.08 (0.003 EXPOSED PAD VIEW AG-AG NB100LVEP222 PACKAGE DIMENSIONS LQFP 52 LEAD EXPOSED PAD PACKAGE CASE 848H-01 ISSUE 0.20 (0.008 PLATING AA -Y- B Ç Ç Ç Ç É É É É AB É É É É ...

Page 13

... BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A2 0.60 0.80 A3 0.20 REF b 0.18 0.30 D 8.00 BSC D2 6.50 6.80 E 8.00 BSC E2 6.50 6.80 e 0.50 BSC K 0.20 --- L 0.30 0.50 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB100LVEP222/D ...

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