nbsg53a ON Semiconductor, nbsg53a Datasheet - Page 2

• Manufacturer Part Number: nbsg53a
• Description: 2.5v/3.3v Sige Selectable Differential Clock And Data D Flip-flop/clock Divider With Reset And Ols
• Manufacturer: ON Semiconductor

Table 1. PIN DESCRIPTION
1. All V
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination
3. When an output level of 400 mV is desired and V
D1,B3
BGA
package bottom (see case drawing) must be attached to a heat−sinking conduit.
voltage, and if no signal is applied then the device will be susceptible to self−oscillation.
N/A
C2
C1
C4
C3
D4
D3
D2
B1
B2
A1
A2
A3
A4
B4
C
D
A
B
Figure 1. BGA−16 Pinout (Top View)
CC
Pin
and V
1
VTD
CLK
CLK
V
CC
QFN
EE
9,16
10
12
13
14
15
11
1
2
3
4
5
6
7
8
−
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
VTCLK
VTCLK
2
D
R
VTCLK
VTCLK
Name
OLS*
CLK
CLK
VTD
VTD
SEL
V
V
EP
D
D
Q
Q
R
CC
EE
V
SEL
V
D
CC
3
EE
VTD
OLS
Q
Q
LVECL, LVCMOS,
LVECL, LVCMOS,
LVCMOS, LVDS,
LVCMOS, LVDS,
LVCMOS, LVDS,
LVCMOS, LVDS,
4
RSECL Output
RSECL Output
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
ECL, CML,
ECL, CML,
ECL, CML,
ECL, CML,
Input
I/O
−
−
−
−
−
−
CC
− V
http://onsemi.com
EE
> 3.0 V, 2KW resistor should be connected from OLS pin to V
Internal 50 W Termination Pin. See Table 4.
Inverted Differential Input.
Noninverted Differential Input.
Internal 50 W Termination Pin. See Table 4.
Internal 50 W termination pin. See Table 4.
Inverted Differential Input.
Noninverted Differential Input.
Internal 50 W Termination Pin. See Table 4.
Positive Supply Voltage
NonInverted Differential Output. Typically Terminated with 50 W Resistor
to V
Inverted Differential Output. Typically Terminated with 50 W Resistor to
V
Negative Supply Voltage
Input Pin for the Output Level Select (OLS). See Table 2.
Select Logic Input. Internal 75 kW to V
Reset D Flip−Flop. Internal 75 kW to V
The Exposed Pad (EP) and the QFN−16 package bottom is thermally
connected to the die for improved heat transfer out of package. The
exposed pad must be attached to a heat−sinking conduit. The pad is not
electrically connected to the die but may be electrically and thermally
connected to V
TT
2
TT
= V
VTCLK
VTCLK
= V
CC
CLK
CLK
CC
− 2 V.
− 2 V.
Figure 2. QFN−16 Pinout (Top View)
EE
1
2
3
4
on the PC board.
VTD
V
16
CC
5
NBSG53A
15
Description
R
D
6
SEL OLS
14
7
D
EE
EE
.
.
VTD
13
8
12
11
10
9
V
Q
Q
V
EE
CC
EE
Exposed Pad
(EP)
.