mm74c76m Fairchild Semiconductor, mm74c76m Datasheet

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mm74c76m

Manufacturer Part Number
mm74c76m
Description
Dual J-k Flip-flops With Clear And Preset
Manufacturer
Fairchild Semiconductor
Datasheet
© 1999 Fairchild Semiconductor Corporation
MM74C73N
MM74C76M
MM74C76N
MM74C73 • MM74C76
Dual J-K Flip-Flops with Clear and Preset
General Description
The MM74C73 and MM74C76 dual J-K flip-flops are mono-
lithic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement transistors.
Each flip-flop has independent J, K, clock and clear inputs
and Q and Q outputs. The MM74C76 flip flops also include
preset inputs and are supplied in 16 pin packages. This
flip-flop is edge sensitive to the clock input and change
state on the negative going transition of the clock pulse.
Clear or preset is independent of the clock and is accom-
plished by a low level on the respective input.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Note: A logic “0” on clear sets Q to logic “0”.
Order Number
Package Number
MM74C73
Top View
M16A
N14A
N16E
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS005884.prf
Features
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
• Computers
Note: A logic “0” on clear sets Q to a logic “0”.
Note: A logic “0” on preset sets Q to a logic “1”.
Supply voltage range:
Tenth power TTL compatible: Drive 2 LPTTL loads
High noise immunity: 0.45 V
Low power: 50 nW (typ.)
Medium speed operation: 10 MHz (typ.)
Package Description
MM74C76
Top View
3V to 15V
October 1987
Revised January 1999
CC
(typ.)
www.fairchildsemi.com

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mm74c76m Summary of contents

Page 1

... Order Number Package Number MM74C73N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM74C76M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74C76N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “ ...

Page 2

Truth Tables bit time before clock pulse n t bit time after clock pulse n 1 Logic Diagrams Transmission Gate www.fairchildsemi.com Preset Clear Q ...

Page 3

Absolute Maximum Ratings Voltage at Any Pin 0. Operating Temperature Range Storage Temperature Power Dissipation Dual-In-Line Small Outline Lead Temperature (Soldering, 10 seconds) Operating V Range CC V (Max Electrical Characteristics Min/Max limits apply across temperature ...

Page 4

AC Electrical Characteristics pF, unless otherwise noted A L Symbol Parameter C Input Capacitance Propagation Delay Time to a pd0 pd1 Logical “0” or Logical “1” from Clock ...

Page 5

AC Test Circuit Typical Applications 74C Compatibility Switching Time Waveforms CMOS to CMOS Ripple Binary Counters Shift Registers Guaranteed Noise Margin as a Function www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow www.fairchildsemi.com Package Number N14A Package Number M16A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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