74hct4024 NXP Semiconductors, 74hct4024 Datasheet - Page 2

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74hct4024

Manufacturer Part Number
74hct4024
Description
7-stage Binary Ripple Counter
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT4024 are high-speed Si-gate CMOS
devices and are pin compatible with the “4024” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4024 are 7-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and seven fully buffered parallel
outputs (Q
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
f
C
C
PHL
max
Output capability: standard
I
7-stage binary ripple counter
I
PD
CC
SYMBOL
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
L
category: MSI
= output frequency in MHz
= input frequency in MHz
(C
PLH
= output load capacitance in pF
P
is used to determine the dynamic power dissipation (P
= supply voltage in V
L
D
0
= C
V
to Q
amb
CC
PD
2
6
propagation delay CP to Q
maximum clock frequency
input capacitance
power dissipation capacitance per package
).
= 25 C; t
V
f
o
CC
) = sum of outputs
2
f
r
i
= t
I
I
f
= GND to V
= GND to V
= 6 ns
PARAMETER
(C
L
V
CC
2
CC
CC
0
f
o
) where:
1.5 V
2
.
The counter advances on the HIGH-to-LOW transition of
CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
APPLICATIONS
D
Frequency dividing circuits
Time delay circuits
C
notes 1 and 2
in W):
L
= 15 pF; V
CONDITIONS
CC
= 5 V
74HC/HCT4024
14
90
3.5
25
HC
Product specification
TYPICAL
14
70
3.5
27
HCT
ns
MHz
pF
pF
UNIT

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