74hct5555 NXP Semiconductors, 74hct5555 Datasheet - Page 4

• Manufacturer Part Number: 74hct5555
• Description: Programmable Delay Timer With Oscillator
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The oscillator configuration allows the
design of RC or crystal oscillator
circuits. The device can operate from
an external clock signal applied to the
RS input (R
connected). The oscillator frequency
is determined by the external timing
components (R
frequency range 1 Hz to 4 MHz
(32 kHz to 20 MHz with crystal
oscillator).
In the HCT version the MR input is
TTL compatible but the RS input has
CMOS input switching levels. The RS
input can be driven by TTL input
levels if RS is tied to V
resistor.
The counter divides the frequency to
obtain a long pulse duration. The
24-stage is digitally programmed via
the select inputs (S
also be used to select the test mode,
which is a convenient way of
functionally testing the counter.
The “5555” is triggered on either the
positive-edge, negative-edge or both.
September 1993
handbook, full pagewidth
Trigger pulse applied to input A for
positive-edge triggering
Programmable delay timer with oscillator
TC
and C
T
and C
0
to S
TC
CC
T
must not be
3
), within the
via a pull-up
). Pin S
14
15
1
4
5
6
RS
OSC
CON
MR
A
B
RTR/RTR
3
can
POWER-ON
RESET
The Schmitt trigger action in the
trigger inputs, transforms slowly
changing input signals into sharply
defined jitter-free output signals and
provides the circuit with excellent
noise immunity.
The OSC CON input is used to select
the oscillator mode, either
continuously running (OSC CON =
HIGH) or triggered start mode (OSC
CON = LOW). The continuously
running mode is selected where a
start-up delay is an undesirable
feature and the triggered start mode
is selected where very low power
consumption is the primary concern.
The start of the programmed time
delay occurs when output Q goes
HIGH (in the triggered start mode, the
previously disabled oscillator will
start-up). After the programmed time
delay, the flip-flop stages are reset
and the output returns to its original
state.
Trigger pulse applied input B for
negative-edge triggering
Trigger pulse applied to inputs A
and B (tied together) for both
positive-edge and negative
triggering.
Fig.3 Functional diagram.
2
R TC
MONOSTABLE
3
C TC
CIRCUITRY
4
CD
CP
24 - STAGE COUNTER
10
S
0
S
11
1
S
12
2
OUTPUT
STAGE
S 3
13
An internal power-on reset is used to
reset all flip-flop stages.
The output pulse can be terminated
by the asynchronous overriding
master reset (MR), this results in all
flip-flop stages being reset. The
output signal is capable of driving a
power transistor. The output time
delay is calculated using the following
formula (minimum time delay is
100 ns):
Once triggered, the output width may
be extended by retriggering the
gated, active HIGH-going input A or
the active LOW-going input B. By
repeating this process, the output
pulse period (Q = HIGH, Q = LOW)
can be made as long as desired. This
mode is selected by RTR/RTR =
HIGH. A LOW on RTR/RTR makes,
once triggered, the outputs (Q, Q)
independent of further transitions of
inputs A and B.
MGA644
Q
Q
1
-- -
f
i
9
7
division ratio (s).
74HC/HCT5555
Product specification