74hct93 NXP Semiconductors, 74hct93 Datasheet - Page 2

• Manufacturer Part Number: 74hct93
• Description: 4-bit Binary Ripple Counter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT93 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT93 are 4-bit binary
ripple counters. The devices consist
of four master-slave flip-flops
internally connected to provide a
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
SYMBOL
t
f
C
C
PHL
max
Various counting modes
Asynchronous master reset
Output capability: standard
I
4-bit binary ripple counter
I
PD
CC
f
C
i
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
PD
= input frequency in MHz; f
L
category: MSI
(C
PLH
= output load capacitance in pF; V
P
is used to determine the dynamic power dissipation (P
L
D
= C
V
CC
amb
PD
PARAMETER
propagation delay CP
maximum clock frequency
input capacitance
power dissipation capacitance per package
2
= 25 C; t
V
f
o
CC
) = sum of outputs
2
f
r
i
= t
I
= GND to V
f
= 6 ns
(C
o
L
= output frequency in MHz
0
V
to Q
CC
divide-by-two section and a
divide-by-eight section. Each section
has a separate clock input (CP
CP
counter on the HIGH-to-LOW clock
transition. State changes of the Q
outputs do not occur simultaneously
because of internal ripple delays.
Therefore, decoded output signals
are subject to decoding spikes and
should not be used for clocks or
strobes.
A gated AND asynchronous master
reset (MR
which overrides both clocks and
resets (clears) all flip-flops.
Since the output from the
divide-by-two section is not internally
connected to the succeeding stages,
CC
2
CC
0
1
; for HCT the condition is V
= supply voltage in V
) to initiate state changes of the
f
o
) where:
1
and MR
2
.
2
) is provided
C
notes 1 and 2
D
L
in W):
= 15 pF; V
CONDITIONS
I
0
= GND to V
and
n
CC
= 5 V
the device may be operated in various
counting modes. In a 4-bit ripple
counter the output Q
connected externally to input CP
The input count pulses are applied to
clock input CP
frequency divisions of 2, 4, 8 and 16
are performed at the Q
Q
table. As a 3-bit ripple counter the
input count pulses are applied to input
CP
Simultaneous frequency divisions of
2, 4 and 8 are available at the Q
and Q
the first flip-flop is available if the reset
function coincides with reset of the
3-bit ripple-through counter.
3
CC
1
outputs as shown in the function
.
3
1.5 V
12
100
3.5
22
outputs. Independent use of
HC
TYPICAL
Product specification
74HC/HCT93
0
. Simultaneous
15
77
3.5
22
HCT
0
must be
0
, Q
1
, Q
ns
MHz
pF
pF
UNIT
2
1
and
1
, Q
.
2