adf4107 Analog Devices, Inc., adf4107 Datasheet
adf4107
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adf4107 Summary of contents
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... Trademarks and registered trademarks are the property of their respective owners. PLL Frequency Synthesizer GENERAL DESCRIPTION The ADF4107 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P ...
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... ADF4107 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Functional Description .................................................................... 9 Reference Input Stage................................................................... 9 RF Input Stage............................................................................... 9 Prescaler (P/P + 1)........................................................................ 9 A and B Counters ......................................................................... 9 R Counter ...................................................................................... 9 REVISION HISTORY 4/07— ...
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... See Figure 25 0.5 V ≤ V ≤ V − 0 0.5 V ≤ V ≤ V − 0 Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V CMOS output chosen I = 500 μ ≤ V ≤ 5 typ T = 25°C A ADF4107 = MAX MIN ...
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... − 20logN −10logF PFD SYNTH TOT 11 The phase noise is measured with the EVAL-ADF4107EB1 evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REF synthesizer ( MHz @ 0 dBm). REFOUT MHz 200 kHz; offset frequency = 1 kHz; f ...
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... ESD rating of <2 kV, and it is ESD sensitive. Proper precautions −0 0 should be taken for handling and assembly. −0 0 −40°C to +85°C ESD CAUTION −65°C to +125°C 150°C 112°C/W 30.4°C/W 260°C 40 sec 6425 303 Rev Page ADF4107 ...
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... MAX R SET = 5.1 kΩ mA. SET CP MAX Rev Page PIN 1 15 MUXOUT CPGND 1 INDICATOR AGND ADF4107 13 DATA AGND 3 12 CLK TOP VIEW NOTES: 1. TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR). Figure 4. Pin Configuration, LFCSP and R ...
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... PFD FREQUENCY = 1MHz –20 LOOP BANDWIDTH = 100kHz RES BANDWIDTH = 10Hz –30 VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS –40 AVERAGES = 10 –50 –60 –70 –80 –83.5dBc/Hz –90 –100 –2kHz –1kHz 6400MHz 1kHz FREQUENCY Figure 10. Phase Noise (6.4 GHz, 1 MHz, 100 kHz) ADF4107 1MHz = 5V 400kHz 2kHz ...
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... ADF4107 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 100Hz FREQUENCY OFFSET FROM 5800MHz CARRIER Figure 11. Integrated Phase Noise (6.4 GHz, 1 MHz, 100 kHz 3V, V REF LEVEL = –10dBm 5mA –10 CP PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz –20 ...
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... ABP1, control the width of the pulse. Use of the minimum antibacklash pulse width is not recommended. See Figure 23. Rev Page × + × REFIN VCO R is the external reference frequency oscillator 13-BIT B COUNTER LOAD PRESCALER P LOAD 6-BIT A COUNTER MODULUS CONTROL N DIVIDER Figure 19. A and B Counters ADF4107 TO PFD ...
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... N DIVIDER Figure 20. PFD Simplified Schematic and Timing (in Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF4107 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 25 shows the full truth table. Figure 21 shows the MUXOUT section in block diagram form ...
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... PD1 F1 MUXOUT CONTROL DB7 DB6 DB5 DB4 DB3 DB2 PD1 F1 ADF4107 CONTROL BITS DB1 DB0 C2 (0) C1 (0) CONTROL BITS DB1 DB0 C2 (0) C1 (1) CONTROL BITS DB1 DB0 C2 (1) C1 (0) CONTROL BITS DB1 DB0 C2 (1) C1 (1) ...
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... ADF4107 REFERENCE COUNTER LATCH MAP TEST BACKLASH RESERVED MODE BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 LDP T2 T1 ABP2 DON’T CARE ABP2 TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION ...
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... PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N × THE REF 2 OUTPUT – P). MIN ADF4107 CONTROL BITS DB2 DB1 DB0 A1 C2 (0) C1 (1) A COUNTER DIVIDE RATIO ...
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... ADF4107 FUNCTION LATCH MAP CURRENT CURRENT PRESCALER SETTING SETTING VALUE 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TC4 CPI6 ...
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... FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH DIVIDER OUTPUT DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND ADF4107 BITS DB0 ...
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... The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4107. Figure 25 shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Fastlock is enabled only when this bit is 1. ...
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... This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. Rev Page ADF4107 was DD ...
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... To have a channel spacing of 1 MHz at the output, the 10 MHz reference input must be divided by 10, using the on-chip reference divider of the ADF4107. The charge pump output of the ADF4107 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45° ...
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... The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4107 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer ...
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... ADF4107BRUZ-REEL –40° 85°C ADF4107BRUZ-REEL7 1 –40° 85°C ADF4107BCP –40° 85°C ADF4107BCP-REEL –40° 85°C ADF4107BCP-REEL7 –40° 85°C 1 ADF4107BCPZ –40° 85°C 1 ADF4107BCPZ-REEL –40° 85°C 1 ADF4107BCPZ-REEL7 –40° 85° RoHS Compliant Part ...