adf4206 Analog Devices, Inc., adf4206 Datasheet - Page 12

• Manufacturer Part Number: adf4206
• Description: Dual Rf Pll Frequency Synthesizers
• Manufacturer: Analog Devices, Inc.

ADF4206/ADF4208
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 25 is a simplified
schematic.
The PFD includes a delay element that sets the width of the
antibacklash phase. The typical value for this in the ADF420x
family is 3 ns. The pulse ensures that there is no dead zone in
the PFD transfer function and minimizes phase noise and
reference spurs.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4206 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by P3, P4, P11, and P12. See Figure 28
and Figure 30. Figure 26 shows the MUXOUT circuit in block
diagram form.
CP OUTPUT
R DIVIDER
N DIVIDER
R DIVIDER
N DIVIDER
HI
HI
Figure 25. PFD Simplified Schematic and Timing (In Lock)
D1
D2
CLR1
CLR2
U1
U2
Q1
Q2
UP
DOWN
ELEMENT
DELAY
U3
CPGND
V
P
CHARGE
PUMP
CP
Rev. A | Page 12 of 24
RF2/RF1 ANALOG LOCK DETECT
LOCK DETECT
MUXOUT can be programmed for analog lock detect. The
N-channel open-drain analog lock detect is operated with an
external pull-up resistor of 10 kΩ nominal. When lock is
detected, it is high with narrow, low going pulses.
INPUT SHIFT REGISTER
The functional block diagram for the ADF420x family is shown
in Figure 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter, and a 17-bit N counter, comprising a 6-bit
A counter and an 11-bit B counter. Data is clocked into the
22-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs (DB1, DB0) as
shown in the timing diagram of Figure 2.
Table 5 is the truth table for these bits.
Table 5. C2, C1 Truth Table
Control Bits
C2
0
0
1
1
RF2 ANALOG LOCK DETECT
RF1 ANALOG LOCK DETECT
RF2 R COUNTER OUTPUT
RF2 N COUNTER OUTPUT
RF1 R COUNTER OUTPUT
RF1 N COUNTER OUTPUT
C1
0
1
0
1
Data Latch
RF2 R counter
RF2 AB counter (and prescaler select)
RF1 R counter
RF1 AB counter (and prescaler select)
Figure 26. MUXOUT Circuit
MUX
CONTROL
DV
DGND
DD
MUXOUT