adf4251 Analog Devices, Inc., adf4251 Datasheet
adf4251
Available stocks
Related parts for adf4251
adf4251 Summary of contents
Page 1
... Dual Fractional-N/Integer-N GENERAL DESCRIPTION The ADF4251 is a dual fractional-N/integer-N frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Both the RF and IF syn- ...
Page 2
... GHz, RF PFD = 10 MHz, MOD = 4095 500 MHz, IF PFD = 200 kHz, REF = 10 MHz The in-band phase noise is measured with the EVAL-ADF4251EB2 Evaluation Board and the HP5500E Phase Noise Test System. The spectrum analyzer provides the REF for the synthesizer ( MHz @ 0 dBm). F ...
Page 3
... CLOCK High Duration ns min CLOCK Low Duration ns min CLOCK to LE Setup Time ns min LE Pulsewidth DB22 DB2 Figure 1. Timing Diagram –3– 10%, GND = 0 V, unless otherwise noted DB1 DB0 (LSB) (CONTROL BIT C2) (CONTROL BIT C1 ADF4251 ...
Page 4
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4251 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 5
... has a value 3 V ± 10 must have the same voltage has a value 3 V ± 10 must have the same voltage –5– ADF4251 /2 and an equivalent input resistance and and DV ...
Page 6
... ADF4251 ADF4251 REF IN MUXOUT CLK DATA LE FROM REFIN 4-BIT R 2 COUNTER DOUBLER FREQUENCY DETECTOR OUTPUT LOCK MUX DETECT FRACTIONAL N RF DIVIDER 24-BIT DATA REGISTER INTEGER N IF DIVIDER FREQUENCY 2 DETECTOR 15-BIT R DOUBLER COUNTER ...
Page 7
... TPC 3. Phase Noise Plot, Lowest Spur Mode, 1.7518 GHz MHz PFD Frequency, OUT 200 kHz Channel Step Resolution TPCs 1–12 attained using EVAL-ADF4252EB1 Evaluation Board; measurements from HP8562E spectrum analyzer. REV. 0 Typical Performance Characteristics–ADF4251 –10 –20 –30 –40 –50 –60 – ...
Page 8
... ADF4251 3V 1.875mA –10 REFERENCE CP PFD FREQUENCY = 20MHz LEVEL = – 4.2dBm CHANNEL STEP = 200kHz –20 LOOP BANDWIDTH = 20kHz FRACTION = 59/100 –30 RBW = 10Hz –40 –50 –60 –70 –80 –90 –100 –2kHz –1kHz 1.7518GHz FREQUENCY TPC 7. Phase Noise Plot, Lowest Noise Mode, 1 ...
Page 9
... ADF4251 LOWEST NOISE MODE LOWEST SPUR MODE 1.435 1.440 1.445 1.450 1.455 FREQUENCY – GHz TPC 16. 400 kHz Spur vs. Frequency * LOWEST NOISE MODE LOWEST SPUR MODE 1.435 1 ...
Page 10
... ADF4251 0 –5 –10 PRESCALER = 4/5 –15 –20 –25 –30 – FREQUENCY – GHz TPC 19. RF Input Sensitivity –0.4 0.1 0.6 IF INPUT FREQUENCY – GHz TPC 20. IF Input Sensitivity –120 –130 –140 – ...
Page 11
... P = the preset modulus of the IF dual modulus (2) prescaler the preset divide ratio of the binary 12-bit counter (3 to 4095), and A = the preset divide ratio of the binary 6-bit swallow counter (0 to 63). F –11– ADF4251 RF N DIVIDER N = INT + FRAC/MOD N-COUNTER THIRD-ORDER FRACTIONAL ...
Page 12
... Hardware Power-Down/Chip Enable In addition to the software power-down methods described on pages 21 and 22, the ADF4251 also has a hardware power- down feature. This is accessed via the Chip Enable (CE) pin. When this pin is Logic High, the device is in normal operation. ...
Page 13
... R11 R10 CONTROL REG RF PHASE IF CP CURRENT RESERVED RESYNC DB15 DB14 DB13 DB12 DB11 DB10 PR3 PR2 T8 T7 PR1 CP3 –13– ADF4251 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB9 DB8 DB7 DB6 DB5 DB4 DB3 ...
Page 14
... ADF4251 8-BIT RF INTEGER VALUE (INT) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 RESERVED 0 RESERVED *WHEN MIN Table III ...
Page 15
... RF R COUNTER R2 R1 DIVIDE RATIO –15– ADF4251 CONTROL BITS DB7 DB6 DB5 DB4 DB3 DB2 DB1 C3 ( (0) INTERPOLATOR MODULUS M2 M1 VALUE (MOD) DIVIDE RATIO ...
Page 16
... ADF4251 RESERVED DB15 DB14 DB13 N3 T3 THESE BITS SHOULD EACH BE SET TO 0 FOR NORMAL OPERATION SETTING CP2 Table V. RF Control Register Map RF CP CURRENT SETTING DB12 DB11 DB10 DB9 DB8 DB7 CP2 CP1 ...
Page 17
... RF N DIVIDER OUTPUT P11 0 THREE-STATE OUTPUT 1 LOGIC LOW DIGITAL LOCK DETECT 1 1 RF/IF DIGITAL LOCK DETECT 0 LOGIC HIGH 1 LOGIC LOW P12 0 –17– ADF4251 CONTROL BITS DB4 DB3 DB2 DB1 DB0 P11 P10 P9 C3 (0) C2 (1) C1 (1) P9 COUNTER RESET 0 DISABLED 1 ENABLED ...
Page 18
... ADF4251 IF PRESCALER* DB19 DB18 DB17 DB23 DB22 DB21 DB20 P15 P14 P13 B12 B11 B10 B9 P14 P13 PRESCALER VALUE 16/ 32/ 64/65 P15 IF CP GAIN 0 DISABLED 1 ENABLED B12 B11 B10 PRESCALER VALUE. B MUST BE GREATER THAN OR EQUAL TO A FOR CONTIGUOUS VALUES Table VII ...
Page 19
... ADF4251 CONTROL BITS DB6 DB5 DB4 DB3 DB2 DB1 DIVIDE RATIO ...
Page 20
... ADF4251 RF PHASE RESERVED RESYNC DB15 DB14 DB13 PR3 PR2 T8 THESE BITS SHOULD BE SET TO 0 FOR NORMAL OPERATION PR3 PR2 PR1 CP3 IF CP2 IF CP1 Table IX. IF Control Register Map ...
Page 21
... WCDMA setup for the different noise and spur settings. RF Counter Reset DB3 is the RF counter reset bit for the ADF4251. When this is 1, the RF synthesizer counters are held in reset. For normal IN operation, this bit should be 0. ...
Page 22
... Table IX shows the input data format for programming this register. Upon initialization, DB15–DB11 should all be set Counter Reset DB3 is the IF counter reset bit for the ADF4251. When this is 1, the IF synthesizer counters are held in reset. For normal operation, this bit should Charge Pump Three-State This bit puts the IF charge pump into three-state mode when pro- grammed ...
Page 23
... The input register remains active and capable of loading and latching data. IF Phase Detector Polarity DB7 in the ADF4251 sets the IF phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set Charge Pump Current Setting DB8, DB9, and DB10 set the IF charge pump current setting ...
Page 24
... Also, there will be spurs at ±200 kHz from the RF carrier. Due to the fractional interpolator architecture used in the ADF4251, spurs will also appear at ±100 kHz from the RF carrier. Harmonics of all spurs mentioned will also appear. With lowest spur setting enabled, the spurs will be attenuated into the noise floor ...
Page 25
... The microconverter is set up for SPI Master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4251 needs (at most) a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer ...
Page 26
... ADSP-21xx Figure 10. ADSP-21xx to ADF4251 Interface ADSP-2181 Interface Figure 10 shows the interface between the ADF4251 and the ADSP-21xx digital signal processor. Each latch of the ADF4251 needs (at most) a 24-bit word. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing ...
Page 27
... Frame Chip Scale Package [LFCSP Body (CP-24) Dimensions shown in millimeters 0.60 MAX 4.0 BSC SQ 0.60 MAX 19 0.50 18 BSC 3.75 TOP BOTTOM BSC SQ VIEW VIEW 0.50 13 0.40 12 0.30 1.00 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.08 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 –27– ADF4251 0.25 MIN PIN 1 INDICATOR 1.70 SQ 0.75 2.50 REF ...
Page 28
–28– ...