adf4360-2 Analog Devices, Inc., adf4360-2 Datasheet
adf4360-2
Available stocks
Related parts for adf4360-2
adf4360-2 Summary of contents
Page 1
... Trademarks and registered trademarks are the property of their respective owners. Integrated Synthesizer and VCO GENERAL DESCRIPTION The ADF4360 fully integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-2 is designed for a center frequency of 2000 MHz. In addition, a divide-by-2 option is available, whereby the user gets an RF output of between 925 MHz and 1085 MHz ...
Page 2
... ADF4360-2 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 Transistor Count........................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Circuit Description........................................................................... 9 Reference Input Section............................................................... 9 Prescaler (P/P + 1)........................................................................ 9 A and B Counters ......................................................................... 9 R Counter ...................................................................................... 9 PFD and Charge Pump ...
Page 3
... V min CMOS output chosen DD 500 μA max 0.4 V max I = 500 μA OL 3.0/3.6 V min/V max typ 2.5 mA typ 24.0 mA typ CORE 29.0 mA typ CORE 3.5 to 11.0 mA typ RF output stage is programmable 7 μA typ Rev Page ADF4360-2 = 4.7 kΩ SET ≤ 2 ≤ 2 ...
Page 4
... ADF4360-2 Parameter 5 RF OUTPUT CHARACTERISTICS VCO Output Frequency VCO Sensitivity Lock Time 6 Frequency Pushing (Open Loop) Frequency Pulling (Open Loop) Harmonic Content (Second) Harmonic Content (Third Output Power Output Power Variation VCO Tuning Range 5 NOISE CHARACTERISTICS 8 VCO Phase-Noise Performance Synthesizer Phase-Noise Floor ...
Page 5
... DB22 DB2 (CONTROL BIT C2) Figure 2. Timing Diagram Rev Page ADF4360 unless otherwise noted. A MIN MAX Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time ...
Page 6
... ADF4360-2 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND VCO VCO DD Digital I/O Voltage to GND Analog I/O Voltage to GND REF to GND IN Operating Temperature Maximum Junction Temperature CSP θ Thermal Impedance JA Paddle Soldered Paddle Not Soldered ...
Page 7
... pin is 0.6 V. The relationship between I SET with a 10 μF capacitor. VCO /2 and a dc equivalent input resistance of DD must have the same value the external loop filter, which in turn drives the CP ADF4360-2 and SET ...
Page 8
... ADF4360-2 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 1 –80 –90 2 –100 –110 –120 –130 –140 –150 –160 –170 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 4. Open-Loop VCO Phase Noise –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 – ...
Page 9
... Two bits in the R counter latch, ABP2 and ABP1, control the width of the pulse (see Table 9 DIVIDER HI N DIVIDER R DIVIDER N DIVIDER CP OUTPUT Figure 12. PFD Simplified Schematic and Timing (In Lock) Rev Page ADF4360 13-BIT B COUNTER LOAD PRESCALER P/P+1 LOAD 5-BIT A MODULUS COUNTER CONTROL N DIVIDER Figure 11 ...
Page 10
... The ADF4360 family contains linearization circuitry to minimize any variation of the product of I Rev Page Data Latch Control Latch R Counter N Counter (A and B) Test Mode Latch ) and resultant V TUNE 1800 1900 2000 2100 2200 2300 FREQUENCY (MHz) , ADF4360-2 TUNE and ...
Page 11
... Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in the control latch. BUFFER/ VCO DIVIDE-BY-2 DD Figure 15. Output Stage ADF4360-2 Rev Page ADF4360 ...
Page 12
... ADF4360-2 LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs determines which latch is programmed. Table 6. Latch Structure PRESCALER CURRENT VALUE SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 ...
Page 13
... DIGITAL LOCK DETECT (ACTIVE HIGH DIVIDER OUTPUT DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND ADF4360-2 CONTROL BITS DB2 DB1 DB0 PC1 C2 (0) C1 (0) CORE POWER LEVEL 5mA 10mA 15mA 20mA DD ...
Page 14
... ADF4360-2 Table 8. N Counter Latch DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DIV2 CPG B13 B12 B11 B10 DIVSEL B13 B12 B11 (FUNCTION LATCH) ...
Page 15
... R13 R12 .......... .......... .......... .......... .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... .......... .......... .......... ADF4360-2 CONTROL BITS DB2 DB1 DB0 R1 C2 (0) C1 (1) DIVIDE RATIO 16380 16381 16382 16383 ...
Page 16
... ADF4360-2 may not achieve lock. If the recommended interval is inserted and the N counter latch is programmed, the band select logic can choose the correct frequency band, and the part locks to the correct frequency ...
Page 17
... Hardware Power-Up/Power-Down If the ADF4360-2 is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, the part locks at the correct frequency because it is already in the correct frequency band. The lock time depends on the value of capacitance on the C pin, which is < ...
Page 18
... ADF4360-2 CONTROL LATCH With (C2, C1) = (0, 0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. Prescaler Value In the ADF4360 family, P2 and P1 in the control latch set the prescaler values. Power-Down DB21 (PD2) and DB20 (PD1) provide programmable power- down modes ...
Page 19
... R counter is by default the value used to clock the band select logic. If this value is too high (>1 MHz), a divider can be switched on to divide the R counter output to a smaller value (see Table 9). Reserved Bits DB23 to DB22 are spare bits that are reserved. They should be programmed to 0. Rev Page ADF4360-2 ...
Page 20
... Hz to 100 kHz) of the LO in this configuration is 2.1°. The AD8349 The optimum LO power can be software programmed on the ADF4360-2, which allows levels from −13 dBm to −6 dBm from each output. The RF output is designed to drive a 50 Ω load but must be ac- coupled, as shown in Figure 17. If the I and Q inputs are driven in quadrature p-p signals, the resulting output power from the modulator is approximately 2 dBm ...
Page 21
... FIXED FREQUENCY LO Figure 18 shows the ADF4360-2 used as a fixed frequency LO at 2.0 GHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz. The maximum PFD frequency of the ADF4360 MHz. Because using a larger PFD frequency allows the use of a smaller N, the in-band phase noise is reduced to as low as possible, – ...
Page 22
... The user should connect the printed circuit thermal pad to AGND. This is internally connected to AGND. OUTPUT MATCHING There are a number of ways to match the output of the ADF4360-2 for optimum operation; the most basic is to use a 50 Ω resistor bypass capacitor of 100 pF is VCO connected in series, as shown in Figure 21 ...
Page 23
... Temperature Range ADF4360-2BCP −40°C to +85°C ADF4360-2BCPRL −40°C to +85°C ADF4360-2BCPRL7 −40°C to +85°C ADF4360-2BCPZ 1 −40°C to +85°C 1 ADF4360-2BCPZRL −40°C to +85°C 1 ADF4360-2BCPZRL7 −40°C to +85°C EVAL-ADF4360-2EB1 Pb-free model. 4.00 BSC SQ 0.60 MAX 0.50 BSC TOP 3.75 VIEW BSC SQ ...
Page 24
... ADF4360-2 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04436– ...