adf4351 Analog Devices, Inc., adf4351 Datasheet - Page 16

• Manufacturer Part Number: adf4351
• Description: Wideband Synthesizer With Integrated Vco Preliminary Technical Data Adf4351
• Manufacturer: Analog Devices, Inc.

ADF4351
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
L1
0
0
1
1
M3
0
0
0
0
1
1
1
1
0
L2
0
1
0
1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
M2
0
0
1
1
0
0
1
1
0
0
NOISE MODE
LOW NOISE MODE
RESERVED
RESERVED
LOW SPUR MODE
NOISE AND
LOW SPUR
L2
M1
0
1
0
1
0
1
0
1
MODES
0
LOW
L1
OUTPUT
THREE-STATE OUTPUT
DV
DGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
0
RESERVED
DD
M3
0
MUXOUT
F4
0
1
M2
0
R10
0
0
.
.
.
1
1
1
1
BAND SELECT
CLOCK MODE
LOW
HIGH
M1
RD2
0
1
0
R9
RD2
0
0
1
1
1
1
.
.
.
REFERENCE
DOUBLER
DISABLED
ENABLED
F4
RD1
0
1
RD1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
F3
0
1
REFERENCE DIVIDE BY 2
DISABLED
ENABLED
F3
R10
ANTI-BACKLASH
PULSE WIDTH
6 ns (FRAC-N)
3 ns (INT_N)
R2
F2
0
1
0
1
0
0
1
1
.
.
.
F2
R9
R1
CHARGE
CANCELLATION
DISABLED
ENABLED
1
0
0
1
0
1
.
.
.
R8
0
C2
0
0
1
1
R DIVIDER (R)
1
2
.
.
.
1020
1021
1022
1023
R7
F1
0
1
0
C1
0
1
0
1
10-BIT R COUNTER
R6
CYCLE SLIP
REDUCTION
DISABLED
ENABLED
F1
Figure 26. Register 2 (R2)
Figure 27. Register 3 (R3)
CLOCK DIVIDER MODE
CLOCK DIVIDER OFF
FASTLOCK ENABLE
RESYNC ENABLE
RESERVED
Rev. PrC | Page 16 of 28
R5
0
R4
CP4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
MODE
CLK
DIV
D1
0
1
DBR
R3
C1
CP3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DOUBLEBUFFER
R4 DB22-20
DISABLED
ENABLED
R2
D12
CP2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R1
D11
D1
D12
0
0
0
0
.
.
.
1
1
1
1
CP1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D10
CP4
D11
0
0
0
0
.
.
.
1
1
1
1
I CP (mA)
5.1kΩ
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
D9
CURRENT
CP3
CHARGE
SETTING
12-BIT CLOCK DIVIDER VALUE
PUMP
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
D8
CP2
U6
0
1
Preliminary Technical Data
D2
0
0
1
1
.
.
.
0
0
1
1
U4
0
1
CP1
U5
0
1
D7
LDF
FRAC-N
INT-N
PD POLARITY
NEGATIVE
POSITIVE
D1
0
1
0
1
.
.
.
0
1
0
1
U6
D6
LDP
10ns
6ns
U5
D5
CLOCK DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
U4
D4
U3
D3
U3
0
1
U2
U2
0
1
D2
POWER DOWN
DISABLED
ENABLED
U1
U1
0
1
CP
THREE-STATE
DISABLED
ENABLED
DB3
D1
C3(0) C2(1) C1(0)
COUNTER
RESET
DISABLED
ENABLED
C3(0) C2(1) C1(1)
CONTROL
DB2
BITS
DB1
CONTROL
BITS
DB1
DB0
DB0