mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 28
![no-image](/images/no-image-200.jpg)
mc145156
Manufacturer Part Number
mc145156
Description
Pll Frequency Synthesizer Family
Manufacturer
Lansdale Semiconductor, Inc.
Datasheet
1.MC145156.pdf
(35 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC145156
Manufacturer:
MOT
Quantity:
3 242
Company:
Part Number:
MC145156
Manufacturer:
JRC
Quantity:
3 250
Part Number:
mc145156DW2
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Company:
Part Number:
mc145156P
Manufacturer:
MOT
Quantity:
5 510
Company:
Part Number:
mc145156P
Manufacturer:
MAXIM
Quantity:
5 510
Company:
Part Number:
mc145156P1
Manufacturer:
MOT
Quantity:
5 510
ML1451xx
Page 28 of 35
NOTE: Sometimes R 1 is split into two series resistors, each R 1
DEFINITIONS:
RECOMMENDED READING:
Damping Factor:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase – Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase – Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
for a typical design w n (Natural Frequency)
N = Total Division Ratio in feedback loop
K φ (Phase Detector Gain) = V DD /4
K φ (Phase Detector Gain) = V DD /2
K VCO (VCO Gain) =
1987.
filter φ V and φ R . The value of C C should be such that the corner frequency of this network does not significantly affect ω n .
The φ R and φ V outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
A)
B)
C)
PD out –
PD out
PD out
φ R
φ V
φ R –
φ V –
φ R –
φ V –
ζ ≅
1
2π∆f VCO
∆V VCO
R 1
R 1
R 1
R 1
PHASE–LOCKED LOOP – LOW–PASS FILTER DESIGN
C
R 2
C
C
π
π
for PD out
for φ V and φ R
R 2
R 2
+ A
_
VCO
VCO
2πfr
10
DESIGN CONSIDERATIONS
C
(at phase detector input).
www.lansdale.com
VCO
÷
2. A capacitor C C is then placed from the midpoint to ground to further
F(s) =
F(s) =
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =
ω n =
ω n =
ω n =
ζ =
ζ =
ζ =
0.5 ω n
(R
2K φ K VCO
R 2 sC + 1
ω n R 2 C
R 1 sC + 1
1 + R 2 )sC + 1
R 1 sC
Nω n
K φ K VCO
2
K φ K VCO
NC(R 1 + R 2 )
R 2 sC + 1
1
NCR 1
NR 1 C
K φ K VCO
(
R 2 C +
K φ K VCO
LANSDALE Semiconductor, Inc.
N
)
Issue A