mc145146dw2 Lansdale Semiconductor, Inc., mc145146dw2 Datasheet - Page 6

• Manufacturer Part Number: mc145146dw2
• Description: 4?bit Data Bus Input Pll Frequency Synthesizer
• Manufacturer: Lansdale Semiconductor, Inc.

ML145146
INPUT PINS
D0 - D3
Data Inputs (Pins 2, 1, 20, 19)
latches when the ST input is in the high state. D3 (Pin 19) is
the most significant bit.
f in
Frequency Input (Pin 3)
from loop VCO and is AC coupled into Pin 3. For larger
amplitude signals (standard CMOS – logic levels) DC coupling
may be used.
OSC in /OSC out
Reference Oscillator Input/Output (Pins 7 and 8)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSC in to ground and OSC out to ground. OSC in
may also serve as input for an externally–generated reference
signal. This signal is typically AC coupled to OSC in , but for
larger amplitude signals (standard CMOS–logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSC out .
A0 - A2
Address Inputs (Pins 9, 10, 11)
information on the data input lines. The addresses refer to the
following latches.
ST
Strobe Transfer (Pin 12)
latch. The falling edge of strobe latches data into the latch.
This pin should normally be held low to avoid loading latches
with invalid data.
PDout
Single–ended Phase Detector Output (Pin 5)
signal.
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Information at these inputs is transferred to the internal
Input to ÷N portion of synthesizer f in is typically derived
These pins form an on–chip reference oscillator when con-
A0, A1 and A2 are used to define which latch receives the
The rising edge of strobe transfers data into the addressed
Three–state output of phase detector for use as loop error
Frequency f V >f R or f V Leading: Negative Pulses
Frequency f V <f R or f V Lagging: Negative Pulses
Frequency f V =f R and Phase Coincidence: High–Impedance
A2
0
0
0
0
1
1
1
1
State
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Selected
Latch 0
Latch 1
Latch 2
Latch 3
Latch 4
Latch 5
Latch 6
Latch 7
PIN DESCRIPTIONS
OUTPUT PINS
Reference Bits
Reference Bits
Reference Bits
Function
÷ A Bits
÷ A Bits
÷ N Bits
÷ N Bits
÷ N Bits
D0 D1
0
4
0
4
8
0
4
8
1
5
1
5
9
1
5
9
D2
10
—
2
6
2
5
2
6
D3
—
—
11
3
3
7
3
7
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LD
Lock Detector (Pin 13)
frequency). Pulses low when loop is out of lock.
MC
Modulus Control (Pin 14)
controlling an external dual–modulus prescaler. The modulus
control level is low at beginning of a count cycle and remains
low until the ÷A counter has counted down from its pro-
grammed value. At this time, modulus control goes high and
remains high until the ÷N counter has counted the rest of the
way down from its programmed value (N – A additional count-
er since both ÷N and ÷A are counting down during the first
portion of the cycle). Modulus control is then set back low, the
counters preset to their respective programmed values, and the
above sequence repeated. This provides for a total programma-
ble divide value (N T ) = N • P ÷ A where P and P ÷ 1 represent
the dual–modulus prescaler divide values respectively for high
and low modulus control levels. N the number programmed
into the ÷N counter and A the number programmed into the
÷A counter.
f V
÷N Counter Output (Pin 15)
connected to the phase detector input. With this output avail-
able, the ÷N counter can be used independently.
φ V , φ R
Phase Detector Outpiuts (Pins 16 adn 17)
a loop error signal. A single–ended output is also available for
this purpose (see PD out ).
leading, then error information is provided by φ V pulsing low
φ R remains essentially high.
lagging, then error information is provided by φ R pulsing low
φ V remains essentially high.
φ V and φ R remain high except for a small minimum time peri-
od when both pulse low in phase.
f R
÷R Counter Output (Pin 18)
nected to the phase detector input. With this output available,
the ÷ R counter can be used independently.
V SS
Ground (Pin 4)
V DD
Positive Power Supply (Pin 6)
with respect to V SS .
High level when loop is locked (f R , f V of same phase and
Signal generated by the on–chip control logic circuitry for
This pin is the output of the ÷N counter that is internallly
These phase detector outputs can be combined externally for
If frequency f V is greater than f R or if the phase of f V is
If the frequency f V is less than f R or if the phase of f V is
If the frequency of f V = f R and both are in phase, then both
This is the output of the ÷ R counter that is internally con-
Circuit Ground
The positive supply voltage may range from 3.0 to 9.0 V
POWER SUPPLY PINS
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