74vhc221a Fairchild Semiconductor, 74vhc221a Datasheet - Page 3

• Manufacturer Part Number: 74vhc221a
• Description: Dual Non-retriggerable Monostable Multivibrator
• Manufacturer: Fairchild Semiconductor

Timing Chart
Functional Description
1. Stand-by State
2. Trigger Operation
The external capacitor (Cx) is fully charged to V
the Stand-by State. That means, before triggering, the
Q
Cx node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply current
is only leakage current.
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling signal;
and third, where the A input is LOW and the B input is
HIGH, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C1 and
C2 start operating, and Q
capacitor discharges through Q
the Rx/Cx node drops. If the Rx/Cx voltage level falls to
the internal reference voltage V
becomes LOW. The flip-flop is then reset and Q
off. At that moment C1 stops but C2 continues operat-
ing.
After Q
rising at a rate determined by the time constant of
external capacitor Cx and resistor Rx.
P
and Q
N
turns off, the voltage at the Rx/Cx node starts
N
transistors which are connected to the Rx/
N
is turned on. The external
N
ref
. The voltage level at
L, the output of C1
N
CC
turns
in
3
3. Reset Operation
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of Rx/Cx changes from falling
to rising. When Rx/Cx reaches the internal reference
voltage V
put Q goes LOW and C2 stops its operation. That
means, after triggering, when the voltage level of the
Rx/Cx node reaches V
MONOSTABLE state.
With large values of Cx and Rx, and ignoring the dis-
charge time of the capacitor and internal delays of the
IC, the width of the output pulse, t
lows:
t
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q out-
put is held LOW and the trigger control F/F is reset.
Also, Q
This means if CLR is set LOW, the IC goes into a wait
state.
W
(OUT)
p
turns on and Cx is charged rapidly to V
ref
H, the output of C2 becomes LOW, the out-
1.0 Cx Rx
ref
H, the IC returns to its
W
www.fairchildsemi.com
(OUT), is as fol-
CC
.