MC14013B
Dual Type D Flip−Flop
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each flip−flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flip−flops for counter and toggle applications.
Features
•
•
•
•
•
•
•
•
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2006
Symbol
V
I
The MC14013B dual type D flip−flop is constructed with MOS
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
low; information is transferred to the output only on the
positive−going edge of the clock pulse
Schottky TTL Load Over the Rated Temperature Range
in
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge−Clocked Flip−Flop Design
Logic state is retained indefinitely with clock level either high or
Capable of Driving Two Low−power TTL Loads or One Low−power
Pin−for−Pin Replacement for CD4013B
Pb−Free Packages are Available
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
SS
SS
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
(Note: Microdot may be in either location)
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
G or G
CASE 948G
CASE 751A
SOEIAJ−14
TSSOP−14
DT SUFFIX
CASE 646
CASE 965
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−14
SOIC−14
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
14
1
14
14
1
1
MC14013BCP
DIAGRAMS
AWLYYWWG
14
MARKING
MC14013B
1
AWLYWW
MC14013B/D
ALYWG
14013BG
ALYW G
013B
14
G