nb2304a ON Semiconductor, nb2304a Datasheet - Page 6

• Manufacturer Part Number: nb2304a
• Description: 3.3 V Zero Delay Clock Buffer
• Manufacturer: ON Semiconductor

Zero Delay and Skew Control
outputs must be equally loaded.
OUTPUT
OUTPUT
-1000
-1500
For applications requiring zero input-output delay, all
1500
1000
-500
500
OUTPUT LOAD DIFFERENCE: FBK LOAD - CLKA/CLKB LOAD (pF)
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
-30 -25 -20 -15 -10
0
Figure 6. Output - Output Skew
1.4 V
t
Figure 4. Duty Cycle Timing
5
1.4 V
CLKA/CLKB Pins
t
2
1.4 V
FBK_Device 1
FBK_Device 2
1.4 V
-5
t
1
0
5
1.4 V
10
t
7
15
V
Figure 8. Device - Device Skew
2
DD
SWITCHING WAVEFORMS
20
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25
V
NB2304A
2
DD
30
OUTPUT
6
can be driven from any of the four available output pins. The
output driving the FBK pin will be driving a total load of
7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input output delay. This is shown in Figure 3.
outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are
required, use Figure 3 to calculate loading differences
between the feedback output and remaining outputs. For
zero output-output skew, be sure to load outputs equally.
To close the feedback loop of the NB2304A, the FBK pin
For applications requiring zero input-output delay, all
OUTPUT
INPUT
Figure 5. All Outputs Rise/Fall Time
t
0.8 V
3
2.0 V
Figure 7. Input - Output Propagation Delay
t
6
V
2
DD
V
2.0 V
2
DD
0.8 V
t
4
0 V
3.3 V