nb7n017m ON Semiconductor, nb7n017m Datasheet
nb7n017m
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nb7n017m Summary of contents
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... The differential inputs contain 50 W termination resistors to VT pads and all differential inputs accept RSECL, ECL, LVDS, LVCMOS, LVTTL, and CML. Internally, the NB7N017M uses a > 3.5 GHz 8–bit programmable down counter. A select pin, SEL, is used to select between two words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGb respectively ...
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... NB7N017M PLa 2 Pa0 3 Pa1 4 5 Pa2 NB7N017M 7 Pa3 Pa4 Pa5 10 Pa6 11 12 Pa7 13 NC Figure 1. Pinout (Top View) http://onsemi.com PLb Pb0 37 36 Pb1 Pb2 Pb3 Pb4 30 Pb5 29 Pb6 28 Pb7 NC 27 ...
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... The NC pins are electrically connected to the die and must be left open. 5. CML outputs require 50 W receiver termination resistor the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. NB7N017M Default Single/Differential State (Notes 1 and 2) − ...
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... Count pulse, load counter from REGa Count pulse, load counter from REGb Hold X − Don’t Care H − HIGH L − LOW Z − Rising Edge NB7N017M Table 3. SEL Truth Table LOW HIGH Pa3/Pb3 Pa2/Pb2 Pa1/Pb1 ...
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... CLK CLK = VTCLK VTCLK = INTERNAL D INTERNAL NB7N017M Figure 2. Input Structure Figure 3. Output Structure http://onsemi.com INTERNAL Q INTERNAL = ...
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... Internal Input Pulldown Resistor (MR, PLa, PLb) Internal Input Pullup Resistor (Pa[0:7], Pb[0:7]) ESD Protection Moisture Sensitivity (Note 7) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 7. For additional information, see Application Note AND8003/D. NB7N017M Counter_State [7:0] GENERATOR MUX_OUT[7:0] MR Pb_INT[7:0] 8−BIT REGb PLb Pb[7:0] Figure 4 ...
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... Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 8. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). NB7N017M Condition ...
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... CMR EE CMR differential input signal. 11. Input and output parameters vary 1:1 with V 12. All loading with 13. V min varies 1:1 with IHCMR EE IHCMR input signal. NB7N017M 3.465 −40°C Min Typ Max Min 170 200 230 170 ...
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... V CMR EE CMR differential input signal. 16. Input and output parameters vary 1:1 with V 17. All loading with 18. V min varies 1:1 with IHCMR EE IHCMR input signal. NB7N017M −40°C Min Typ Max Min 170 200 230 170 V V ...
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... V − INPP CC EE 21. Device−to−Device skew for identical transitions at identical V 400 300 200 100 0 0 Figure 5. Output Voltage Amplitude (V NB7N017M = −3.465 V to −3 3 3.465 −40°C Min Typ Max Min 300 400 ...
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... Application Information All NB7N017M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are PECL Driver Recommended R Values 5.0 V 290 W V 3.3 V 150 2 ...
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... XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX X − Don’t Care H − HIGH L − LOW NB7N017M Z No Connect No Connect V REF Pb PLb SEL 00000100 00000100 ...
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... XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX 0 XXXXXXXX L XXXXXXXX X − Don’t Care H − HIGH L − LOW NB7N017M Pb PLb SEL ...
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... NB7N017M MR Pa[7:0] 05 PLa Pa_INT[7:0] Pb[7:0] 04 PLb Pb_INT[7:0] SEL CE CLK CLK_INT TC_INT TC Figure 10. Device Timing Diagram for Table 12 MR CLK CE CLK_INT Figure 11. Timing Diagram for CE Input http://onsemi.com ...
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... NB7N017M MR delay CLK PLa Pa[7:0] 0B d=12 d=12 TC[7:0] Figure 12. Timing Diagram for PLa / PLb Inputs (SEL is Low) MR delay CLK PLa Pa[7:0] d=12 d=256 d=256 TC[7:0] Figure 13. Timing Diagram for PLa / PLb Inputs (Before Critical Rising Edge of CLK) (SEL is Low) MR delay CLK PLa (hex) Pa[7:0] d=256 d=256 d=256 d=256 TC[7:0] Figure 14. Timing Diagram for PLa / PLb Inputs ...
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... NB7N017M MR CLK SEL Pa[7:0] Pb[7:0] PLa PLb d=4 d=4 TC[7:0] Figure 15. Timing Diagram for SEL Input (Before Critical Rising Edge of CLK) MR CLK SEL Pa[7:0] Pb[7:0] PLa PLb d=4 d=4 TC[7:0] Figure 16. Timing Diagram for SEL Input (After Critical Rising Edge of CLK) MR CLK Pa[7: PLa Pa_INT[7:0] 255 2 Pb/PLb have the same functionality as Pa/PLa ...
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... Single−Ended thmax IHmax V ILmax IHmin V thmin V ILmin GND Figure 21. V Diagram th NB7N017M V INPP V OUTPP t PHL t PLH Figure 18. AC Reference Measurement CMmax V CMR V CMmax GND http://onsemi.com (CLK) − V (CLK (TC) − V ...
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... Q Figure 24. Typical Termination for 16 mA Output Drive and Device Evaluation ORDERING INFORMATION Device NB7N017MMN NB7N017MMNG NB7N017MMNR2 NB7N017MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB7N017M + Figure 23 ...
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... COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A2 0.60 0.80 A3 0.20 REF b 0.18 0.30 D 8.00 BSC D2 6.50 6.80 E 8.00 BSC E2 6.50 6.80 e 0.50 BSC K 0.20 −−− L 0.30 0.50 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB7N017M/D ...