74lvth162373 Fairchild Semiconductor, 74lvth162373 Datasheet

74lvth162373

Manufacturer Part Number

74lvth162373

Description

Low Voltage 16-bit Transparent Latch With 3-state Outputs And 25ohm Series Resistors In The Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74LVTH162373.pdf (7 pages)

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74LVTH162373MEA

74LVTH162373MEX

(Note 1)

74LVTH162373MTD

74LVTH162373MTX

(Note 1)

74LVTH162373

Low Voltage 16-Bit Transparent Latch with

3-STATE Outputs and

25: Series Resistors in the Outputs

General Description

The LVTH162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear transparent to the data when the Latch Enable (LE)

is HIGH. When LE is LOW, the data that meets the setup

time is latched. Data appears on the bus when the Output

Enable (OE) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

The LVTH162373 is designed with equivalent 25

resistance in both the HIGH and LOW states of the output.

This design reduces line noise in applications such as

memory address drivers, clock drivers, and bus transceiv-

ers/transmitters.

The LVTH162373 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These latches are designed for low-voltage (3.3V) V

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVTH162373 is fabricated

with an advanced BiCMOS technology to achieve high

speed operation similar to 5V ABT while maintaining a low

power dissipation.

Ordering Code:

Note 1: Use this Order Number to receive devices in Tape and Reel.

Logic Symbol

Order Number

Package

Number

MS48A

MTD48

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

[TUBES]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

[TAPE and REEL]

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TUBES]

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TAPE and REEL]

DS500354

series

Features

Input and output interface capability to systems at

5V V

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs

Live insertion/extraction permitted

Power Up/Down high impedance provides glitch-free

bus loading

Outputs include equivalent series resistance of 25

make external termination resistors unnecessary and

reduce overshoot and undershoot

Functionally compatible with the 74 series 16373

Latch-up performance exceeds 500 mA

ESD performance:

Human-body model

Machine model

Charged-device model

Package Description

200V

2000V

1000V

October 2000

Revised June 2005

www.fairchildsemi.com

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