74lvt74 NXP Semiconductors, 74lvt74 Datasheet - Page 3

• Manufacturer Part Number: 74lvt74
• Description: 3.3v Dual D-type Flip-flop
• Manufacturer: NXP Semiconductors

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Philips Semiconductors
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
NOTES:
RECOMMENDED OPERATING CONDITIONS
1996 Aug 28
V
GND = Pin 7
SYMBOL
SYMBOL
SYMBOL
CC
3.3V Dual D-type flip-flop
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
V
T
I
I
V
V
T
= Pin 14
I
OUT
OUT
V
I
SD
RD
CP
V
I
I
OUT
t/ v
amb
V
OK
V
OH
OL
CC
IK
stg
CC
D
IH
IL
I
I
4, 10
1, 13
2, 12
3, 11
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output current
DC out ut current
Storage temperature range
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
PARAMETER
3
3
1, 2
PARAMETER
PARAMETER
5, 9
6, 8
SF00048
Q
Q
Output in Off or High state
3
Output in High state
Output in Low state
H = High voltage level
h = High voltage level one setup time prior to low-to-high
L = Low voltage level
l
NC= No change from the previous setup
X = Don’t care
*
CONDITIONS
FUNCTION TABLE
NOTES:
SD
H
H
H
H
L
L
= Low voltage level one setup time prior to low-to-high
= Low-to-high clock transition
= Not low-to-high clock transition
= This setup is unstable and will change when either set
V
V
O
I
< 0
clock transition
clock transition
or reset return to the high level.
< 0
RD
H
H
H
H
L
L
INPUTS
CP
X
X
X
D
X
X
X
X
h
l
MIN
–40
2.7
2.0
OUTPUTS
NC
0
Q
H
H
H
L
L
–0.5 to +4.6
–0.5 to +7.0
–0.5 to +7.0
–65 to 150
RATING
LIMITS
–50
–50
–32
64
NC
Q
H
H
H
L
L
MAX
–20
+85
3.6
5.5
0.8
32
10
Asynchronous set
Asynchronous reset
Undetermined*
Load “1”
Load “0”
Hold
Product specification
74LVT74
OPERATING
MODE
UNIT
UNIT
UNIT
ns/V
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
C
C