74lvq373 STMicroelectronics, 74lvq373 Datasheet

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74lvq373

Manufacturer Part Number
74lvq373
Description
Low Voltage Cmos Octal D-type Latch With 3 State Outputs Non Inverting
Manufacturer
STMicroelectronics
Datasheet

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74lvq373TTR
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DESCRIPTION
The 74LVQ373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type latch are controlled by a latch
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
HIGH SPEED:
t
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
LOW NOISE:
V
75 TRANSMISSION LINE OUTPUT DRIVE
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
PD
CC
PLH
OH
OLP
CC
= 5.8 ns (TYP.) at V
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 3.6V (1.2V Data Retention)
= 0.4V (TYP.) at V
t
PHL
OL
= 12mA (MIN) at V
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
A
CC
=25°C
CC
= 3.3 V
WITH 3 STATE OUTPUTS NON INVERTING
= 3.3V
CC
= 3.0 V
2
MOS
Table 1: Order Codes
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
SOP
74LVQ373
Rev. 5
74LVQ373MTR
74LVQ373TTR
TSSOP
T & R
1/13

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74lvq373 Summary of contents

Page 1

... PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C technology ideal for low power and low noise 3 ...

Page 2

... Figure 2: Input And Output Equivalent Circuit Table 3: Truth Table Don’t Care High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level Figure 3: Logic Diagram 2/13 Table 2: Pin Description PIN N° 12, ...

Page 3

... Supply Voltage (note Input Voltage I V Output Voltage O T Operating Temperature op Input Rise and Fall Time V dt/dv 1) Truth Table guaranteed: 1. from 0. Parameter Parameter = 3.0V (note 2) CC 74LVQ373 Value Unit - 400 mA -65 to +150 ° ...

Page 4

... Table 6: DC Specifications Symbol Parameter V High Level Input IH Voltage 3 Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I High Impedance OZ Output Leakage Current I Quiescent Supply CC Current I Dynamic Output OLD Current (note OHD ...

Page 5

... A Typ. Max. Min. Max. Min. 7.2 11.5 13.5 5.8 9.0 10.5 7.2 11.5 13.5 5.8 9.0 10.5 8.7 14.0 16.0 7.4 11.5 13.5 8.5 14.0 16.0 7.5 11.5 13.5 2.0 5.0 6.0 1.5 4.0 4.0 0.0 4.0 4.5 0.0 3.0 3.0 0.0 1.5 1.5 0.0 1.5 1.5 0.5 1.0 1.0 0.5 1.0 1 PHLm PHLn Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min CC(opr 74LVQ373 Unit Max. 15.5 ns 12.0 15.5 ns 12.0 18.5 ns 15.5 18.5 ns 15.5 6.0 ns 4.0 4.5 ns 3.0 1.5 ns 1.5 1.0 ns 1.0 Unit Max (per Latch 5/13 ...

Page 6

... Figure 4: Test Circuit PLH PHL PZL PLZ PZH PHZ C = 50pF or equivalent (includes jig and probe capacitance 500 or equivalent pulse generator (typically OUT Figure 5: Waveform - Propagation Delays, LE Minimum Pulse Width Setup And Hold Times (f=1MHz; 50% duty cycle) ...

Page 7

... Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle) 74LVQ373 7/13 ...

Page 8

... DIM. MIN. A 2.35 A1 0.1 B 0.33 C 0.23 D 12. 10.00 h 0.25 L 0.4 k 0° ddd 8/13 SO-20 MECHANICAL DATA mm. TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 1.27 10.65 0.75 1.27 8° 0.100 inch MIN. TYP. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.394 0.010 0.016 0° 0016022D MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.419 0.030 0.050 8° ...

Page 9

... K 0˚ PIN 1 IDENTIFICATION 1 mm. TYP MAX. 1.2 0.15 1 1.05 0.30 0.20 6.5 6.6 6.4 6.6 4.4 4.48 0.65 BSC 8˚ 0.60 0. 74LVQ373 inch MIN. TYP. 0.002 0.004 0.031 0.039 0.007 0.004 0.252 0.256 0.244 0.252 0.169 0.173 0.0256 BSC 0˚ 0.018 0.024 0087225C MAX. 0.047 0.006 0.041 0.012 ...

Page 10

... DIM. MIN 12 10.8 Bo 13.2 Ko 3.1 Po 3.9 P 11.9 10/13 Tape & Reel SO-20 MECHANICAL DATA mm. TYP MAX. 330 13.2 30.4 11 13.4 3.3 4.1 12.1 inch MIN. TYP. 12.992 0.504 0.795 2.362 0.425 0.520 0.122 0.153 0.468 MAX. 0.519 1.197 0.433 0.528 0.130 0.161 0.476 ...

Page 11

... Tape & Reel TSSOP20 MECHANICAL DATA DIM. MIN 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 7 0.268 7.1 0.272 1.9 0.067 4.1 0.153 12.1 0.468 74LVQ373 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.276 0.280 0.075 0.161 0.476 11/13 ...

Page 12

... Table 10: Revision History Date Revision 29-Jul-2004 5 12/13 Description of Changes Ordering Codes Revision - pag. 1. ...

Page 13

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