74lv257 NXP Semiconductors, 74lv257 Datasheet - Page 2

• Manufacturer Part Number: 74lv257
• Description: Quad 2-input Multiplexer 3-state
• Manufacturer: NXP Semiconductors

1. C
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
NOTE:
ORDERING INFORMATION
PIN CONFIGURATION
t
C
C
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
1998 May 20
PHL
SYMBOL
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
Typical V
T
Typical V
T
Non-inverting data path
Output capability: bus driver
I
Quad 2-input multiplexer (3-State)
I
PD
CC
P
f
f
amb
amb
i
o
PD
D
= input frequency in MHz; C
/t
= output frequency in MHz; V
(C
category: MSI
PLH
= C
= 25 C
= 25 C
L
is used to determine the dynamic power dissipation (P
PD
OLP
OHV
V
PACKAGES
CC
amb
Propagation delay
nl
S to nY
Input capacitance
Power dissipation capacitance per gate
V
(output ground bounce) < 0.8 V at V
2
(output V
0
CC
, nl
= 25 C; t
GND
f
1I
2
1I
2l
2l
2Y
o
IY
1
S
) = sum of the outputs.
0
1
0
1
to nY
f
i
2
3
4
5
6
7
8
1
) (C
OH
r
= t
undershoot) > 2 V at V
PARAMETER
f
L
2.5 ns
L
= output load capacitance in pF;
CC
V
CC
CC
= supply voltage in V;
2
TEMPERATURE RANGE
SV00636
= 2.7 V and V
16
15
14
12
11
10
13
9
f
o
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
) where:
V
OE
4l
4l
4Y
3l
3l
3Y
CC
0
1
0
1
CC
CC
= 3.3 V,
= 3.3 V,
CC
= 3.6 V
C
V
V
D
L
CC
I
= GND to V
= 15 pF;
in W)
= 3.3 V
OUTSIDE NORTH AMERICA
2
CONDITIONS
DESCRIPTION
The 74LV257 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT257.
The 74LV257 is a quad 2-input multiplexer with 3-state outputs, which
select 4 bits of data from two sources and are controlled by a common
data select input (S). The data inputs from source 0 (1l
selected when input S is LOW and the data inputs from source 1 (1l
to 4l
to 4Y) in true (non-inverting) from the selected inputs. The 74LV257 is
the logic implementation of a 4-pole, 2-position switch, where the
position of the switch is determined by the logic levels applied to S.
The outputs are forced to a high impedance OFF-state when OE is
HIGH.
The logic equations for the outputs are:
1Y = OE
2Y = OE
3Y = OE
4Y = OE
CC
PIN DESCRIPTION
1
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
8
15
16
74LV257 DB
74LV257 PW
1
74LV257 N
74LV257 D
NUMBER
1
) are selected when S in HIGH. Data appears at the outputs (1Y
PIN
(1l
(2l
(3l
(4l
1
1
1
1
S
1l
1l
1Y to 4Y
GND
OE
V
SYMBOL
S + 1l
S + 2l
S + 3l
S + 4l
CC
0
1
to 4l
to 4l
0
0
0
0
0
1
NORTH AMERICA
S)
S)
S)
S)
74LV257PW DH
Common data select input
Data inputs from source 0
Data inputs from source 1
3-state multiplexer outputs
Ground (0 V)
3-State output enable input
(active LOW)
Positive supply voltage
74LV257 DB
74LV257 N
74LV257 D
TYPICAL
3.5
10
14
30
FUNCTION
Product specification
74LV257
PKG. DWG. #
853-1985 19420
SOT109-1
SOT338-1
SOT403-1
0
SOT38-4
to 4l
UNIT
pF
pF
0
ns
) are
1