m48t512y STMicroelectronics, m48t512y Datasheet - Page 7

• Manufacturer Part Number: m48t512y
• Description: 5.0 Or 3.3v, 4 Mbit 512 Kbit X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

READ Mode
The M48T512Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 19 Ad-
dress Inputs defines which one of the 524,288
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Ac-
cess Time (t
nal is stable, providing the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
Figure 5. READ Mode AC Waveforms
Note: WE = High.
Table 3. READ Mode AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
Symbol
t
t
t
t
GLQX
EHQZ
GHQZ
ELQX
t
t
t
t
t
GLQV
AXQX
AVQV
ELQV
AVAV
2. C
(2)
(2)
(2)
(2)
L
= 5pF.
A0-A18
E
G
DQ0-DQ7
AVQV
READ Cycle Time
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
) after the last address input sig-
Parameter
(1)
tAVQV
tELQX
tELQV
tGLQX
A
= 0 to 70°C; V
tGLQV
tAVAV
VALID
CC
of the Chip Enable Access Times (t
Enable Access Time (t
three-state Data I/O signals is controlled by E and
G. If the outputs are activated before t
data lines will be driven to an indeterminate state
until t
while E and G remain active, output data will re-
main valid for Output Data Hold Time (t
will go indeterminate until the next Address Ac-
cess.
= 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
Min
70
10
5
5
M48T512Y
AVQV
–70
DATA OUT
. If the Address Inputs are changed
Max
70
70
40
25
25
tAXQX
tGHQZ
GLQV
M48T512Y, M48T512V*
Min
85
5
5
5
M48T512V
). The state of the eight
–85
tEHQZ
ELQV
AI02389
Max
85
85
55
30
30
) or Output
AVQV
AXQX
Unit
, the
) but
ns
ns
ns
ns
ns
ns
ns
ns
ns
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