max5477eud Maxim Integrated Products, Inc., max5477eud Datasheet - Page 10

• Manufacturer Part Number: max5477eud
• Description: Dual, 256-tap, Nonvolatile, I2c-interface, Digital Potentiometers
• Manufacturer: Maxim Integrated Products, Inc.

V
the EEPROM and to update the wiper position from
either the value in the EEPROM or directly from the I
interface. Connecting WP to GND increases the supply
current by 19.6µA (max).
The MAX5477/MAX5478/MAX5479 operate as slave
devices that send and receive data through an I
SMBus™-compatible 2-wire serial interface. The inter-
face uses a serial data access (SDA) line and a serial
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master, typically a
microcontroller, initiates all data transfers to the
MAX5477/MAX5478/MAX5479, and generates the SCL
clock that synchronizes the data transfer (Figure 1).
The MAX5477/MAX5478/MAX5479 SDA line operates
as both an input and an open-drain output. The SDA
line requires a pullup resistor, typically 4.7kΩ. The
MAX5477/MAX5478/MAX5479 SCL line operates only
as an input. The SCL line requires a pullup resistor (typ-
ically 4.7kΩ) if there are multiple masters on the 2-wire
Dual, 256-Tap, Nonvolatile, I
Digital Potentiometers
Table 1. Slave Addresses
Figure 5. Bit Transfer
SMBus is a trademark of Intel Corporation.
10
DD
SDA
SCL
GND
GND
GND
GND
. Connect WP to GND to allow write commands to
V
V
V
V
A2
______________________________________________________________________________________
DD
DD
DD
DD
ADDRESS INPUTS
DATA STABLE,
DATA VALID
GND
GND
GND
GND
V
V
V
V
A1
DD
DD
DD
DD
CHANGE OF
DATA ALLOWED
GND
GND
GND
GND
V
V
V
V
A0
DD
DD
DD
DD
Serial Addressing
SLAVE ADDRESS
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
2
C-/
2
C
interface, or if the master in a single-master system has
an open-drain SCL output. SCL and SDA should not
exceed V
open-drain drivers.
Each transmission consists of a START (S) condition
(Figure 3) sent by a master, followed by the
MAX5477/MAX5478/MAX5479 7-bit slave address plus
the
byte, and finally a STOP (P) condition (Figure 3).
Both SCL and SDA remain high when the interface is
not busy. A master controller signals the beginning of a
transmission with a START condition by transitioning
SDA from high to low while SCL is high. The master
controller issues a STOP condition by transitioning the
SDA from low to high while SCL is high, when it finishes
communicating with the slave. The bus is then free for
another transmission (Figure 3).
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 5).
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure
6). Thus, each byte transferred effectively requires 9 bits.
The master controller generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line remains stable low during
the high period of the clock pulse.
The MAX5477/MAX5478/MAX5479 have a 7-bit-long
slave address (Figure 4). The 8th bit following the 7-bit
Figure 6. Acknowledge
SDA
SCL
CONDITION
NOP/W bit (Figure 4), 1 command byte and 1 data
START
2
C-Interface,
DD
in a mixed-voltage system, despite the
1
2
Start and Stop Conditions
NOT ACKNOWLEDGE
ACKNOWLEDGE
ACKNOWLEDGMENT
8
CLOCK PULSE FOR
Slave Address
Acknowledge
Bit Transfer
9