max509bcwpt Maxim Integrated Products, Inc., max509bcwpt Datasheet

max509bcwpt

Manufacturer Part Number

max509bcwpt

Description

Max509, Max510 Quad, Serial, 8-bit Dacs With Rail-to-rail Outputs

Manufacturer

Maxim Integrated Products, Inc.

Datasheet

1.MAX509BCWPT.pdf (20 pages)

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The MAX509/MAX510 are quad, serial-input, 8-bit volt-

age-output digital-to-analog converters (DACs). They

operate with a single +5V supply or dual ±5V supplies.

Internal, precision buffers swing rail-to-rail. The refer-

ence input range includes both supply rails.

The MAX509 has four separate reference inputs, allow-

ing each DAC's full-scale range to be set independently.

20-pin DIP, SSOP, and SO packages are available. The

MAX510 is identical to the MAX509 except it has two ref-

erence inputs, each shared by two DACs. The MAX510

is housed in space-saving 16-pin DIP and SO packages.

The serial interface is double-buffered: A 12-bit input

shift register is followed by four 8-bit buffer registers and

four 8-bit DAC registers. A 12-bit serial word is used to

load data into each register. Both input and DAC regis-

ters can be updated independently or simultaneously

with single software commands. Two additional asyn-

chronous control pins provide simultaneous updating

(LDAC) or clearing (CLR) of input and DAC registers.

The interface is compatible with Microwire

QSPI

compatible. A buffered data output provides for read-

back or daisy-chaining of serial devices.

19-0155; Rev 2; 1/96

_______________Functional Diagrams

Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

_______________General Description

DOUT

Functional Diagrams continued at end of data sheet.

CS DIN SCLK

CONTROL

CLR

12-BIT

SHIFT

. All digital inputs and outputs are TTL/CMOS

LDAC

CONTROL

DECODE

AGND

DGND V

INPUT

REG A

INPUT

REG B

INPUT

REG C

INPUT

REG D

________________________________________________________________ Maxim Integrated Products

MAX509

REG C

REG D

REG A

REG B

DAC

REFB

REFC

DAC A

DAC C

REFA

DAC B

DAC D

REFD

and SPI/

OUTD

OUTC

OUTA

OUTB

with Rail-to-Rail Outputs

Quad, Serial 8-Bit DACs

____________________________Features

Ordering Information continued on last page.

* Dice are specified at +25°C, DC parameters only.

**Contact factory for availability and processing to MIL-STD-883.

_________________Pin Configurations

______________Ordering Information

MAX509ACPP

MAX509BCPP

MAX509ACWP

MAX509BCWP

MAX509ACAP

MAX509BCAP

MAX509BC/D

Single +5V or Dual ±5V Supply Operation

Output Buffer Amplifiers Swing Rail-to-Rail

Reference Input Range Includes Both Supply Rails

Calibrated Offset, Gain, and Linearity (1LSB TUE)

10MHz Serial Interface, Compatible with SPI, QSPI

(CPOL = CPHA = 0) and Microwire

Double-Buffered Registers for Synchronous

Updating

Serial Data Output for Daisy-Chaining

Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

Pin Configurations continued at end of data sheet.

TOP VIEW

PART

DGND

OUTB

OUTA

AGND

DOUT

LDAC

REFB

REFA

N.C.

TEMP. RANGE

0°C to +70°C

DIP/SO/SSOP

MAX509

PIN-PACKAGE

20 Plastic DIP

20 Wide SO

20 SSOP

Dice*

OUTC

OUTD

REFC

REFD

N.C.

DIN

SCLK

CLR

(LSB)

±1

±1 1/2

±1

±1 1/2

±1

±1 1/2

TUE

Related parts for max509bcwpt

max509bcwpt Summary of contents

Page 1

Rev 2; 1/96 _______________General Description The MAX509/MAX510 are quad, serial-input, 8-bit volt- age-output digital-to-analog converters (DACs). They operate with a single +5V supply or dual ±5V supplies. Internal, precision buffers swing rail-to-rail. The refer- ence input range includes both ...

Page 2

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ABSOLUTE MAXIMUM RATINGS V to DGND ..............................................................-0.3V, + AGND...............................................................-0.3V, + DGND ...............................................................-6V, +0. AGND ...............................................................-6V, +0. .................................................................-0.3V, +12V DD SS ...

Page 3

ELECTRICAL CHARACTERISTICS (continued +5V ±10 -5.5V, V REF = 4V, AGND = DGND = 0V 10kΩ 100pF MIN to T MAX , ...

Page 4

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ELECTRICAL CHARACTERISTICS (continued +5V ±10 -5.5V, V REF = 4V, AGND = DGND = 0V 10kΩ 100pF ...

Page 5

Operating Characteristics (T = +25°C, unless otherwise noted.) A OUTPUT SINK CURRENT vs OUT VREF = + GND = 0V SS ALL DIGITAL ...

Page 6

Quad, Serial 8-DACs with Rail-to-Rail Outputs ____________________________Typical Operating Characteristics (continued +25°C, unless otherwise noted.) A ZERO-CODE ERROR vs. NEGATIVE SUPPLY VOLTAGE 5 +5V DD 4.8 VREF = +4V 4.6 4.4 4.2 4.0 3.8 3.6 3.4 0 ...

Page 7

Operating Characteristics (continued +25°C, unless otherwise noted.) A CLOCK FEEDTHROUGH A = SCLK, 333kHz B = OUT_, 10mV/div TIMEBASE = 2 s/div NEGATIVE SETTLING TIME (V = AGND 100mV 1µ DIGITAL INPUT, 5V/div ...

Page 8

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ______________________________________________________________Pin Description PIN NAME MAX509 MAX510 1 1 OUTB DAC B Voltage Output 2 2 OUTA DAC A Voltage Output Negative Power Supply -5V ±10%. Connect to AGND ...

Page 9

Description Serial Interface At power-on, the serial interface and all DACs are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK's rising edge. The MAX509/MAX510 communicate with microproces- sors through a ...

Page 10

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs CS t CSS t CSH0 SCLK DIN DOUT LDAC NOTE: TIMING SPECIFICATION t IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY. CLL Figure 2. Detailed Serial Interface ...

Page 11

Serial Input Data Format and Control Codes The 12-bit serial input format shown in Figure 3 com- prises two DAC address bits (A1, A0), two control bits (C1, C0) and eight bits of data (D0...D7). The 4-bit address/control code configures ...

Page 12

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs Set DOUT Phase – SCLK Falling (Mode (LDAC = x) This command resets DOUT to transition ...

Page 13

MAX509 SCLK SCLK MAX510 DIN DOUT DIN CS CS MAX509 SCLK SCLK MAX510 DIN DIN CS CS Figure 6. Daisy-chained or individual MAX509/MAX510s are simultaneously updated by bringing CS high. Only three wires are required. DIN SCLK LDAC CS1 CS2 ...

Page 14

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs REF_ AGND SHOWN FOR ALL 1 ON DAC Figure 8. DAC Simplified Circuit Diagram If multiple devices share a common DIN line, Figure ...

Page 15

SYSTEM GND OUTC OUTD V DD REFC REFD Figure 9. Suggested MAX509 PC Board Layout for Minimizing Crosstalk (Bottom View) Unipolar-Output, 2-Quadrant Multiplication In unipolar operation, the output voltages and the refer- ence input(s) are the same polarity. Figures 11 ...

Page 16

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs REFERENCE INPUTS ( + REFA REFB REFC REFD DAC A DAC B SERIAL INTERFACE NOT SHOWN DAC C DAC D V AGND ...

Page 17

SERIAL INTERFACE NOT SHOWN 0 330k 0.1% MAX873 +2. ICL7611A Figure 14. MAX509 AGND Bias Circuit (Negative Offset) 4-Quadrant Multiplication Each DAC output may be configured for 4-quadrant multiplication using Figure 16 and 17's ...

Page 18

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs +5V SERIAL INTERFACE 0.1 F NOT SHOWN 2 R1 330k 0.1% MAX873 6 +2. ICL7611A -5V Figure 15. MAX510 AGND Bias Circuit (Negative Offset) REFERENCE INPUTS (V ...

Page 19

REFERENCE INPUTS 4 13 DAC A SERIAL DAC B INTERFACE NOT SHOWN DAC C DAC 0.1 F AGND OR -5V Figure 17. MAX510 Bipolar Output Circuit __Functional Diagrams (continued) CLR DGND V AGND V REFB REFA DOUT ...

Page 20

Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs _Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE MAX509AEPP -40°C to +85°C 20 Plastic DIP MAX509BEPP -40°C to +85°C 20 Plastic DIP MAX509AEWP -40°C to +85°C 20 Wide SO MAX509BEWP -40°C to +85°C 20 ...

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