max5938 Maxim Integrated Products, Inc., max5938 Datasheet - Page 22

• Manufacturer Part Number: max5938
• Description: Max5938 -48v Hot-swap Controller With Vin Step Immunity, No Rsense, And Overvoltage Protection
• Manufacturer: Maxim Integrated Products, Inc.

3) When GATE reaches the gate threshold voltage of
4) When V
OV GATE Cycle to Fault management:
1) Same as step 1 above. [GATE pulldown]
2) Same as step 2 above. [GATE turn-on]
3) Same as step 3 above. [V
4) If GATE ramps to 90% of full enhancement and
GATE is a complex output structure and its condition at
any moment is dependent on various timing
sequences in response to multiple inputs. A diode to
V
sions, the states are:
1) Power-off with 2V clamp.
2) 8Ω pulldown to V
3) Floating with 16V clamp [prior to GATE ramp].
4) 52µA current source with 16V clamp [GATE ramp].
5) Pullup to internal 10V supply with 16V clamp [full
As mentioned previously in the Setting the Circuit-
Breaker and Short-Circuit Thresholds section, the AC
response from V
sitics of the load. This is especially true for the load
capacitor in conjunction with the power MOSFET’s
R
LSR) and the power MOSFET’s R
eled as a heavily damped second-order system. As
such, this system functions as a bandpass filter from
-48V Hot-Swap Controller with V
No R
22
EE
DS(ON)
V
pulled to V
PGOOD is deasserted. [Fault management]
the power MOSFET, V
down toward V
below the MOSFET threshold, the MOSFET is off
and V
stant of the load. [V
rapidly pulled to full enhancement and the OV GATE
cycle is complete. [Full enhancement]
enhancement].
OUT
prevents negative excursions. For positive excur-
______________________________________________________________________________________
a. Continuous during startup delay and during
b. Pulsed following detected step or OV
. The load capacitor (with parasitic ESR and
OUT
remains above 74% V
SENSE
fault conditions.
condition.
OUT
will droop depending on the RC time con-
EE
ramps below 74% V
IN
, fault management is initiated, and
EE
to V
EE.
. In the interval where GATE is
OUT
Step Monitor Component
OUT
, and Overvoltage Protection
ramp]
OUT
is dependent on the para-
OUT
Selection Analysis
begins to ramp back
ramp]
CB
DS(ON)
, GATE is rapidly
Appendix B
CB
GATE Output
, the GATE is
can be mod-
V
ramp. STEP_MON lags the V
RC response, while V
second-order response.
Given a positive V
approximate response of V
where τ
Equation 1 is a simplification for the overdampened
second-order response of the load to a ramp input, τ
= C
the load capacitor to transfer dV/dt current to the fully
enhanced power MOSFET’s R
time constant of the load (τ
sitic series inductance and resistance of the capacitor
and board interconnect. To characterize the load
dynamic response to V
empirically with a few tests.
Similarly, the response of STEP_MON to a V
where τ
For proper step detection, V
STEP
V
ed in the application). It is impossible to give a fixed set
of design guidelines that rigidly apply over the wide
array of applications using the MAX5938. There are,
however, limiting conditions and recommendations that
should be observed.
One limiting condition that must be observed is to
ensure that the STEP_MON time constant, τ
so low that at the lowest ramp rate, the anticipated
STEP
τ
voltage at STEP_MON if the V
indefinitely. A related condition is setting the
STEP_MON voltage below STEP
gin, ∆V
both I
τ
gin with worst-case I
The margin of V
set when R
Setting the Circuit-Breaker and Short-Circuit Thresholds
section. This margin may be lower at one of the temper-
ature extremes and if so, that value should be used in
the following discussion. These margins will be called
STEP
STEP_MON
IN
OUT
to V
LOAD
V
TH
STEP_MON
TH
reaching V
STEP_OS
= τ
C
STEP
STEP_MON
OUT
V
prior to V
cannot be obtained. The product (dV/dt) x
OUT
= C
STEP_MON,MAX
x R
, use the 9.2µA limit to ensure sufficient mar-
CB_ADJ
limiting the ability of V
= R
(t) = (dV/dt) x τ
LOAD
DS(ON)
IN
(±8%) and R
(t) = (dV/dt) x τ
STEP_MON
OUT
CB
IN
OUT
+ R
, to accommodate the tolerance of
+ 10µA x R
x R
(or overall V
Step Immunity,
STEP_OS
ramp with a ramp rate of dV/dt, the
is selected as described in the
and corresponds to the ability of
(with respect to V
DS(ON)
DS(ON)
reaching V
OUT
, is the maximum differential
IN
OUT
L,eqv
x C
lags with an overdamped
C
.
ramps, determine τ
STEP_MON
x I
.
IN
STEP_MON
IN
x (1-e
STEP_MON.
STEP_MON
STEP
to V
LOAD
DS(ON)
) accounts for the para-
IN
TH
ramp with a first-order
ramp were to continue
SC
OUT
ramp rates anticipat-
IN
with adequate mar-
(-t / τL,eqv)
x (1-e
or within 1.4ms of
is:
. The equivalent
. In determining
to follow the V
SC
(-t / τSTEP)
must exceed
(Equation 2)
(Equation 1)
and V
IN
STEP
)
ramp is:
, is not
CB
L,eqv
)
) is
IN
C