max5109 Maxim Integrated Products, Inc., max5109 Datasheet - Page 14

• Manufacturer Part Number: max5109
• Description: Max5109 Nonvolatile, Dual, 8-bit Dacs With 2-wire Serial Interface
• Manufacturer: Maxim Integrated Products, Inc.

Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial
Interface
Separate nonvolatile and volatile control registers store
and update the state of the mute/power-down mode for
each DAC. Tables 7 and 8 show how to access and
control each register. Register access is gained by set-
ting control bits C3–C0 to 0100. Bits C5 and C4 indi-
cate whether the nonvolatile or volatile control register
is accessed. The volatile register maintains data while
the device remains powered. The nonvolatile register
maintains data even after power is removed. The
MAX5109 starts up (power first applied) by transferring
the mute/power-down modes from the nonvolatile con-
Table 5. Volatile and Nonvolatile Read
Selection
Table 7. Mute/Power-Down Operation
*See Mute/Power-Down Control Register (Table 8).
Table 8. Mute/Power-Down Control Register
X = Don’t care.
14
CONTROLLING
FUNCTION
Write VCTL
Write NVCTL
Write VCTL
and NVCTL
Transfer
NVCTL to
VCTL
Mute/Power-Down Register and Operation
NONVOLATILE
COMMAND
______________________________________________________________________________________
(NV)
0
1
S
T
A
R
T
S
S
S
S
VOLATILE
(MSB)
ADDRESS
D7
(V)
X
1
0
BYTE
R/
W
0
0
0
0
Read from VREG_
Read from NVREG_
A
C
K
D6
X
C
7
0
0
0
0
FUNCTION
C
6
0
0
0
0
COMMAND BYTE
Mute DAC1
C
5
0
1
1
0
C
4
1
0
1
0
D5
C
3
0
0
0
0
C
2
1
1
1
1
Mute DAC0
C
0
0
0
0
1
BIT IN REGISTER
C
0
0
0
0
D4
0
trol register to the volatile control register. The non-
volatile control register is set to 00 hex at the factory.
Power-on reset (POR) circuitry controls the initialization
of the MAX5109. A POR loads the volatile registers with
the data stored in the nonvolatile registers.
This initialization period takes 500µs (typ). During this
time, the DAC outputs are held in mute mode. At the
completion of the initialization period, the DAC outputs
update in accordance with the data stored in the non-
volatile registers.
Table 6. DAC Read Selection
A
C
K
R3
0
0
MSB
D
7
D
6
Control register*
Control register*
Control register*
Control register*
R2
D3
0
0
DATA BYTE
D
5
X
D
4
D
3
R1
0
0
D
2
D2
D
1
X
LSB
R0
0
1
D
0
A
C
K
Power-down
DAC1
Power-On Reset
D1
FUNCTION
DAC0
DAC1
STOP
P
P
P
P
Power-down
(LSB)
DAC0
D0