max5140ipg Maxim Integrated Products, Inc., max5140ipg Datasheet - Page 8

• Manufacturer Part Number: max5140ipg
• Description: 8-bit, Ultra-high-speed Dac
• Manufacturer: Maxim Integrated Products, Inc.

To be registered synchronously, control and data inputs
must be present at the input pins for a specific setup
time (t
CONV’s rising edge. Setup and hold times are not impor-
tant in asynchronous mode. The minimum pulse widths
high (t
become the limiting factors (Figure 4).
The video controls produce the output levels needed
for horizontal blanking, frame synchronization, etc., to
be compatible with video-system standards as
described in RS-343-A. Table 1 shows the video-
control effects on the analog output. Internal logic gov-
erns blank, sync, and force high so that they override
the data inputs as needed in video applications. Sync
overrides both the data and other controls to produce
full negative video output (Figure 5).
Reference-white, video-level output is provided by
force high, which drives the internal digital data to full-
scale output (100IRE units). Bright gives an additional
10% of full-scale value to the output level. This function
can be used in graphic displays for highlighting menus,
8-Bit, Ultra-High-Speed DAC
Figure 4. Timing Diagram
8
_______________________________________________________________________________________
PWH
s
) before and a specific hold time (t
) and low (t
CONV
-1.3 V
CONV
-1.3 V
OUT -
OUT +
PWL
), as well as settling time,
t
S
H
Data Control
) after
Inputs
t
DST
t
PWH
t
cursors, or warning messages. If the devices are used
in nonvideo applications, the video controls can be left
open.
For best performance, the clock should be differentially
ECL driven by using CONV and CONV (Figure 6).
Driving the clock in this manner minimizes clock noise
and power-supply/output intermodulation. The clock’s
rising edge synchronizes the data and control inputs to
the MAX5140. Since CONV determines the actual
switching threshold of CONV, the clock can be driven
single-ended by connecting a bias voltage to CONV.
This bias voltage sets the converter clock’s switching
threshold.
The MAX5140 has two analog outputs that are high-
impedance, complementary current sinks. The outputs
vary in proportion to the input data, controls, and refer-
ence-current values so that the full-scale output can be
changed by setting I
DSC
t
H
1/2 LSB
t
PWL
t
SI
Set
.
1/2 LSB
Analog Outputs
Convert Clock