max5264 Maxim Integrated Products, Inc., max5264 Datasheet - Page 10

• Manufacturer Part Number: max5264
• Description: Max5264 Octal, 14-bit, Voltage-output Dac With Parallel Interface For Ate
• Manufacturer: Maxim Integrated Products, Inc.

Octal, 14-Bit Voltage-Output DAC
with Parallel Interface for ATE
All digital inputs are compatible with both TTL and
CMOS logic. The MAX5264 interfaces with micro-
processors using a data bus at least 13 bits wide. The
interface is double buffered, allowing simultaneous
updating of all DACs. There are two latches for each
DAC (see Functional Diagram): an input latch that
receives data from the data bus, and a DAC latch that
receives data from the input latch. Address lines A0,
A1, and A2 select which DAC’s input latch receives
data from the data bus as shown in Table 2. Both the
input latches and the DAC latches are transparent
when CS, WR, and LD are all low. Any change of
D0–D13 during this condition appears at the output
instantly. Transfer data from the input latches to the
DAC latches by asserting the asynchronous LD signal.
Each DAC’s analog output reflects the data held in its
DAC latch. All control inputs are level triggered. Table 3
is an interface truth table.
Table 2. MAX5264 DAC Addressing
Table 3. Interface Truth Table
X = Don’t care
10
CLR
X
X
X
X
X
0
1
A2
0
0
0
0
1
1
1
1
______________________________________________________________________________________
LD
X
X
X
X
0
1
1
A1
Digital Inputs and Interface Logic
0
0
1
1
0
0
1
1
WR
0
X
1
X
X
X
X
A0
0
1
0
1
0
1
0
1
CS
0
1
X
X
X
X
X
DAC A input latch
DAC B input latch
DAC C input latch
DAC D input latch
DAC E input latch
DAC F input latch
DAC G input latch
DAC H input latch
Input register transparent
Input register latched
Input register latched
DAC register transparent
DAC register latched
Outputs of DACs at
DUTGND_ _
Outputs of DACs set to volt-
age defined by the DAC
register, the references,
and the corresponding
DUTGND_ _
FUNCTION
FUNCTION
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch, and LD transfers
information from the input latch to the DAC latch. The
input latch is transparent when CS and WR are low,
and the DAC latch is transparent when LD is low. The
address lines (A0, A1, A2) must be valid for the dura-
tion that CS and WR are low (Figure 2) to prevent data
from being inadvertently written to the wrong DAC.
Data is latched within the input latch when either CS or
WR is high.
Taking LD high latches data into the DAC latches. If LD
is brought low when WR and CS are low, the DAC
addressed by A0, A1, and A2 is directly controlled by
the data on D0–D13. This allows the maximum digital
update rate; however, it is sensitive to any glitches or
skew in the input data stream.
The MAX5264 has an asynchronous clear pin (CLR)
that, when asserted, sets all DAC outputs to the voltage
present on their respective DUTGND pins. Deassert
CLR to return the DAC output to its previous voltage.
Note that CLR does not clear any of the internal digital
registers.
The MAX5264 can be used for multiplying applications.
Its reference accepts both DC and AC signals. Since
the reference inputs are unipolar, multiplying operation
is limited to two quadrants. See the graphs in the
Typical Operating Characteristics for dynamic perfor-
mance of the DACs and output buffers.
The MAX5264 uses offset binary coding. A 14-bit two’s
complement code is converted to a 14-bit offset binary
code by adding 2
For typical operation, connect DUTGND to signal
ground, V
shows the relationship between digital code and output
voltage.
The DAC digital code controls each leg of the 14-bit
R-2R ladder. A code of 0x0 connects all legs of the lad-
der to REF-, corresponding to a DAC output voltage
(V
legs of the ladder to REF+, corresponding to a V
approximately equal to REF+.
DAC
) equal to REF-. A code of 0x3FFF connects all
REF
+ to +4.5V, and V
Applications Information
13
= 8192.
Analog Output Voltage
Output Voltage Range
Multiplying Operation
REF
Asynchronous Clear
Digital Code and
Loading the DACs
- to -2.0V. Table 4
Input Write Cycle
DAC