max5883egmtd Maxim Integrated Products, Inc., max5883egmtd Datasheet - Page 13

• Manufacturer Part Number: max5883egmtd
• Description: Max5883 3.3v, 12-bit, 200msps High Dynamic Performance Dac With Cmos Inputs
• Manufacturer: Maxim Integrated Products, Inc.

Figure 8. ACLR for W-CDMA Modulation, Single Carrier
supply decoupling guidelines for high-speed, high-fre-
quency applications should be closely followed. This
reduces EMI and internal crosstalk that can significant-
ly affect the dynamic performance of the MAX5883.
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. High-speed signals should run on lines directly
above the ground plane. Since the MAX5883 has sepa-
rate analog and digital ground buses (AGND,
CLKGND, and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two planes.
Digital signals should be run above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Digital signals should be kept as far
away from sensitive analog inputs, reference input
sense lines, common-mode input, and clock inputs as
practical. A symmetric design of clock input and ana-
log output lines is recommended to minimize 2nd-order
harmonic distortion components and optimize the
DAC’s dynamic performance. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5883 supports three separate power-supply
inputs for analog (AV
(VCLK) circuitry. Each AV
should at least be decoupled with a separate 0.1µF
capacitor as close to the pin as possible and their
opposite ends with the shortest possible connection to
the corresponding ground plane (Figure 10). All three
power-supply voltages should also be decoupled at the
**Thermal efficiency is not the key factor, since the MAX5883 features low-power operation. The exposed pad is the key element to
***Vias connect the land pattern to internal or external copper planes. It is important to connect as many vias as possible to the analog
ensure a solid ground connection between the DAC and the PC board’s analog ground layer.
ground plane to minimize inductance.
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______________________________________________________________________________________
DD
), digital (DV
DD
3.5MHz/div
Performance DAC with CMOS Inputs
3.3V, 12-Bit, 200Msps High Dynamic
, DV
f
f
ACLR = 71dB
CLK
CENTER
DD
= 184.32MHz
, and VCLK input
= 30.72MHz
DD
), and clock
point they enter the PC board with tantalum or elec-
trolytic capacitors. Ferrite beads with additional decou-
pling capacitors forming a pi network could also
improve performance.
The analog and digital power-supply inputs AV
VCLK, and DV
age range of 3.3V ±5%.
The MAX5883 is packaged in a 48-pin QFN-EP
(package code: G4877-1), providing greater design
flexibility, increased thermal efficiency**, and optimized
AC performance of the DAC. The exposed pad (EP)
enables the user to implement grounding techniques,
which are necessary to ensure highest performance
operation. The EP must be soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the PC board with standard infrared (IR)
flow soldering techniques. A specially created land pat-
tern on the PC board, matching the size of the EP (5mm
of the DAC. Designing vias*** into the land area and
implementing large ground planes in the PC board
design allow for highest performance operation of the
DAC. An array of at least 3
per via hole and 1.2mm pitch between via holes) is rec-
ommended for this 48-pin QFN-EP package.
Figure 9. ACLR for W-CDMA Modulation, Four Carriers
5mm), ensures the proper attachment and grounding
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DD
f
f
CLK
CENTER
of the MAX5883 allow a supply volt-
= 184.32MHz
= 30.72MHz
4MHz/div
3 vias ( 0.3mm diameter
ACLR = 67dB
DD
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