max5852etlt Maxim Integrated Products, Inc., max5852etlt Datasheet - Page 16

• Manufacturer Part Number: max5852etlt
• Description: Max5852 Dual, 8-bit, 165msps, Current-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

Dual, 8-Bit, 165Msps, Current-Output DAC
or spurious-free dynamic range. In addition, electro-
magnetic interference (EMI) can either couple into or
be generated by the MAX5852. Observe the grounding
and power-supply decoupling guidelines for high-
speed, high-frequency applications. Follow the power-
supply and filter configuration to realize optimum
dynamic performance.
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. Run high-speed signals on lines directly above the
ground plane. The MAX5852 has separate analog and
digital ground buses (AGND, CGND, and DGND,
respectively). Provide separate analog, digital, and
clock ground sections on the PC board with only one
point connecting the three planes. The ground connec-
tion points should be located underneath the device
and connected to the exposed paddle. Run digital sig-
nals above the digital ground plane and analog/clock
signals above the analog/clock ground plane. Digital
signals should be kept away from sensitive analog,
clock, and reference inputs. Keep digital signal paths
short and metal trace lengths matched to avoid propa-
gation delay and data skew mismatch.
The MAX5852 includes three separate power-supply
inputs: analog (AV
(CV
branch out to three separate power-supply lines (AV
DV
Filter each power-supply line to the respective return
line using LC filters comprising ferrite beads and 10µF
capacitors. Filter each supply input locally with 0.1µF
ceramic capacitors to the respective return lines.
Note: To maintain the dynamic performance of the
Electrical Characteristics, ensure the voltage differ-
ence between DV
exceed 150mV.
40-lead thin QFN-EP:
The MAX5852 is packaged in a 40-pin thin QFN-EP
package, providing greater design flexibility, increased
thermal efficiency, and optimized AC performance of
the DAC. The EP enables the implementation of
grounding techniques, which are necessary to ensure
highest performance operation.
*Vias connect the land pattern to internal or external copper planes.
16
DD
DD
Thermal Characteristics and Packaging
______________________________________________________________________________________
, CV
). Use a single linear regulator power source to
DD
) and returns (AGND, DGND, CGND).
DD
θ
DD
JA
, AV
), digital (DV
= 38°C/W
DD
, and CV
Thermal Resistance
DD
DD
), and clock
does not
DD
,
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the PC board with standard infrared (IR)
flow soldering techniques. A specially created land pat-
tern on the PC board, matching the size of the EP
(4.1mm
grounding of the DAC. Designing vias* into the land
area and implementing large ground planes in the PC
board design allows for highest performance operation
of the DAC. Use an array of 3
ter per via hole and 1.2mm pitch between via holes) for
this 40-pin thin QFN-EP package (package code:
T4066-1).
THD is the ratio of the RMS sum of all essential harmon-
ics (within a Nyquist window) of the input signal to the
fundamental itself. This can be expressed as:
where V
V
monics. The MAX5852 uses the first seven harmonics
for this calculation.
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of their next-largest spectral component. SFDR is usu-
ally measured in dBc with respect to the carrier fre-
quency amplitude or in dBFS with respect to the DAC’s
full-scale range. Depending on its test condition, SFDR
is observed within a predefined window or to Nyquist.
A series of equally spaced tones are applied to the DAC
with one tone removed from the center of the range.
MTPR is defined as the worst-case distortion (usually a
3rd-order harmonic product of the fundamental frequen-
cies), which appears as the largest spur at the frequency
of the missing tone in the sequence. This test can be per-
formed with any number of input tones; however, four and
eight tones are among the most common test conditions
for CDMA- and GSM/EDGE-type applications.
Dynamic Performance Parameter Definitions
N
THD
are the amplitudes of the 2nd through Nth order har-
=
1
is the fundamental amplitude, and V
4.1mm), ensures the proper attachment and
20
×
Spurious-Free Dynamic Range (SFDR)
log






Total Harmonic Distortion (THD)
Multitone Power Ratio (MTPR)


V
2
2
+
V
3
3 vias (≤0.3mm diame-
2
+
V
1
V
4
2
... ...
+
V
2
N
through
2







