max5891egkt4ead Maxim Integrated Products, Inc., max5891egkt4ead Datasheet - Page 8

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max5891egkt4ead

Manufacturer Part Number
max5891egkt4ead
Description
Max5891 16-bit, 600msps, High-dynamic-performance Dac With Lvds Inputs
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
8
46, 48, 50, 52,
54, 56, 58, 60,
47, 49, 51, 53,
55, 57, 59, 62,
15, 20, 23, 24,
14, 21, 22, 25,
13, 42, 43, 44
2, 4, 6, 8, 45,
1, 3, 5, 7, 9,
63, 65, 67
64, 66, 68
27, 30, 33
26, 31, 32
19, 34, 35
_______________________________________________________________________________________
36, 41
37, 40
PIN
10
11
12
16
17
18
28
29
38
39
61
D8N, D7N, D6N, D5N
D3P, D2P, D1P, D0P,
D9P, D8P, D7P, D6P,
D14N, D13N, D12N,
D15P, D14P, D13P,
D12P, D11P, D10P,
D11N, D10N, D9N,
D1N, D0N, D15N,
D4N, D3N, D2N,
D5P, D4P
DACREF
DV
AV
AV
DV
FSADJ
NAME
DGND
AV
CGND
AGND
REFIO
OUTN
OUTP
CLKN
CLKP
N.C.
PD
EP
DD3.3
DD3.3
DD1.8
DD1.8
CLK
Differential Negative LVDS Inputs. Data bits D0–D15 (offset binary format).
Differential Positive LVDS Inputs. Data bits D0–D15 (offset binary format).
Digital Ground. Ground return for DV
Analog Ground. Ground return for AV
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to DGND.
Power-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for
normal operation. PD has an internal 2µA pulldown.
No Connection. Leave floating or connect to AGND.
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to AGND.
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a
0.1µF capacitor to AGND. REFIO can be driven with an external reference source.
Full-Scale Current Adjustment. Connect an external resistor R
DACREF to set the output full-scale current. The output full-scale current is equal to 32 x
V
Current-Set Resistor Return Path. Internally connected to ground, but do not use as
ground connection.
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1µF capacitor to AGND.
Complementary DAC Output. Negative terminal for current output.
DAC Output. Positive terminal for current output.
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to CGND.
Clock Supply Ground
Complementary Converter Clock Input. Negative input terminal for differential converter
clock.
Converter Clock Input. Positive input terminal for differential converter clock.
Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1µF capacitor to DGND.
Exposed Pad. Must be connected to common point for AGND, DGND, and CGND through
a low-impedance path. EP is internally connected to AGND, DGND, and CGND.
REF
/ R
SET
.
DD3.3
DD3.3
FUNCTION
and DV
and AV
DD1.8
DD1.8
.
.
SET
Pin Description
between FSADJ and

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