max5820 Maxim Integrated Products, Inc., max5820 Datasheet - Page 9

• Manufacturer Part Number: max5820
• Description: Max5820 Dual, 8-bit, Low-power, 2-wire, Serial Voltage-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

Figure 2. START and STOP Conditions
Figure 3. Early STOP Conditions
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5820 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5820 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address (Figure 4). When idle, the MAX5820
SDA
SCL
SCL
SDA
SCL
SDA
S
_______________________________________________________________________________________
LEGAL STOP CONDITION
ILLEGAL EARLY STOP CONDITION
START
STOP
Dual, 8-Bit, Low-Power, 2-Wire, Serial
S
ILLEGAL
START
r
Acknowledge Bit (ACK)
STOP
Slave Address
P
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit-by-bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or read-
ing from the MAX5820 (R/W = 0 selects the write condi-
tion, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5820 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5820 has four different factory/user-pro-
grammed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to V
MAX5820s to share the same bus.
In write mode (R/W = 0), data that follows the address
byte controls the MAX5820 (Figure 5). Bits C3–C0 con-
figure the MAX5820 (Table 3). Bits D7–D0 are DAC
data. Bits S3–S0 are sub-bits and are always 0. Input
and DAC registers update on the falling edge of SCL
during the acknowledge bit. Should the write cycle be
prematurely aborted, data is not updated and the write
cycle must be repeated. Figure 6 shows two example-
write data sequences.
The MAX5820 features an extended command mode
that is accessed by setting C3–C0 = 1 and D7–D4 = 0.
Table 2. MAX5820 I
Figure 4. Slave-Address Byte Definition
Figure 5. Command-Byte Definition
DD
MAX5820M
MAX5820M
MAX5820L
MAX5820L
PART
Voltage-Output DAC
S
sets A0 = 1. This feature allows up to four
C3
A6
C2
A5
C1
A4
V
GND
GND
V
V
ADD
C0
DD
DD
2
C Slave Addresses
A3
Extended Command Mode
D7
A2
D6
DEVICE ADDRESS
Write Data Format
A1
D5
0111 000
0111 001
1011 000
1011 001
(A6–A0)
A0
D4
R/W
9