stlc1511 STMicroelectronics, stlc1511 Datasheet
stlc1511
Related parts for stlc1511
stlc1511 Summary of contents
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... GA), a low pass anti-aliasing filter, and a 12-bit Nyquist rate A/D converter. The RxPGA is digitally programmable from 0 to 40dB in 0.5dB steps. 2.0 PACKAGING AND PIN INFORMATION 2.1 STLC1511 Pin Allocation The pinout for the STLC1511 is depicted in Figure ...
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... STLC1511 2.2 Pin Description Table 1. details the pinout assignment for the STLC1511. The following list gives the different pin types for the STLC1511. Table 1. Pin Assignement Pin # Pin Name Pin Type 1 VDDDIG1 VDD 2 CK35M DI 3 DIGREF DO 4 RXSOUT[ RXSOUT[ VSSDIGE1 ...
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... Quiet ground for Tx circuitry ANA Tx positive output ANA Tx negative output VDDCO 5V supply for TxPGA VSSCO Ground for TxPGA VDDA 5V supply for ESD ring VSSA Ground for ESD ring VDDCO 5V supply for DAC VSSCO Ground for DAC ANA DAC reference (2.5V) 0.1uF STLC1511 2 2 3/31 ...
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... This block also gener- ates an accurate current using an external resistor from which all of the STLC1511 circuits are biased. In addition, the bias circuitry also generates a 2.5V ref- erence for the external Vco/Vcxo components and can be used for other external circuits if necessary ...
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... Figure 2. The block diagram of the STLC1511 B and gap/ Bias Gen SIN [1: [1: Shaded blocks are only usabe when the PLL is active. Crystal based external resonator for the CPE Mode, LC based resonator for the CO Oscillator Mode ...
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... STLC1511 Table 2. Receive Path Specifications Unless otherwise noted, typical specifications apply for VCC=5.0Volts, temperature=2 7× C, nominal process and current. Maximum and minimum performance is with VCC ± ±5%, -40 =< T Description Stage Absolute Gain 3 Diff in to Diff out ...
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... STLC1511 =< 105 × C, and worst case process. Units Comments spot noise @30Khz measured single ended nV at RXINP or RXINN ---------- - Hz spot noise @30kHz measured differentially at RXINP/N spot noise @30kHz measured differentially at nV RXDCINP/N ---------- - ...
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... ADC output word to the input voltage at RXINP/RXINN when the input to the Rx path is at 2.4Vp differential measured between RXINP and RXINN. <2>For G.lite the STLC1511 will support both CO and CPE applications. As such it needs to support rates from 30kHz to 120kHz (CO Receive band) and 155kHz to 540kHz (CPE Receive band). ...
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... STLC1511 =< 105 × C, and worst case process. Units Comments Where “D” is the binary dB value in b[11:7] of the control word. Includes Vcc, temperature, process, and frequency variation. dB For a 1 LSB change in the control word at a fixed frequency f (30kHz =< f =< 540kHz) For more than a 1LSB ...
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... STLC1511 Table 3. Transmit Path Specifications Unless otherwise noted, typical specifications apply for VCC=5 Volts, temperature=2 7× C, nominal process and current. Maximum and minimum performance is with VCC ±5%, -40 =< T Description Output Signal to Distortion ratio 7 Two tone 8 DS Multi-tone 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz ...
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... TXOP/TXON when the output from the Tx path is at 2.4Vp differential measured between TXOP and TXON. <2>For G.lite the STLC1511 will support both CO and CPE applications. As such it needs to support rates from 30kHz to 120kHz (CPE Transmit band) and 155kHz to 540kHz (CO Transmit band). 275kHz is roughly in the middle of the required frequency range. ...
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... Central Office (Oscillator Mode) In Oscillator Mode the 2.56MHz reference clock on pin FREF is used as the reference clock for the STLC1511 PLL. This clock is used to lock the LC os- cillator frequency to 88.32MHz which is further divid- ed down to provide the sampling clocks to both the TX and RX converters and passed to the digital ASIC STLC1510 as its PLL reference on the pin DIGREF ...
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... STLC1511 =< 105×C, and worst case process. Units Comments MHz on pin FREF MHz at pin DIGREF MHz Assumes 2% capacitors. mVp msec see CAPTION FIGURE 4 MHz/V on page 14 mA see TITLE 3 3.4.3 on page 16 see TITLE 3 3 ...
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... STLC1511 Figure 3. CO Frequency vs. Tuning Voltage C h arge osc_o utp o sc_ou tn Figure 4. CO Frequency vs. Tuning Voltage 14/ 2. SCN e=100pF C pF L=56nH C v=10pF R b=4k R x=1M ...
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... Figure 5. Oscillator Input Impedence Figure 6. Oscillator Output Impedence STLC1511 15/31 ...
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... STLC1511 3.4.3 Customer Premise Equipment In CPE mode, the STLC1511 provides the amplifier required to power the off-chip crystal oscillator. The crystal oscillator runs at a frequency of 35.328 MHz (series resonant) which is further divided down to provide the sampling clocks to both the TX and RX converters and passed to the STLC1510 as its PLL reference on the pin DIGREF ...
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... Figure 8. CPE Frequency vs. Tuning Voltage 2 180pF 20pF rystal M odel pF STLC1511 SIC C urre eco v ery pF 17/31 ...
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... RXSOUT[1:0] pins. The serial interface also consists of a 35.328MHz clock (CK35M) which is generated in the STLC1510 and is used to retime the Tx data sent to the STLC1511 also used in the STLC1511 to retime 18/31 junction min typ max 3 ...
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... CK ADC 3.6.1 ADC Clip Indicator Normally, the receive signal level is set such that the input to the STLC1511 plus the RxPGA gain will not saturate the input to the ADC converter (for maxi- mum ADC input levels). If the input signal is too large however and causes the ...
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... MHz. The companion DSP chip, STLC1510, sources the 35.328 MHz clock used by the AFE. To minimize the impact of digital noise on the STLC1511, this supplied clock is gated, and is only enabled during data transfers and during reset. The clock does not need to be present in order to re- set the chip ...
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... For a write operation, the data on the DRX pin is latched into the STLC1511 on the negative edge of the DIGCLK signal. The data should change state on the positive edge of the clock. For a read operation, the data on the DTX pin is out- put on the positive edge of the clock on pin DIGCLK ...
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... STLC1511 Table 9. Detailed Register Map: AFE Control Byte 1 Title: AFE Control 1 (Rx PGA Gain) Label: Rx Gain Address: 000 Description: Rx PGA Gain Setting Bit Label Bit(s) RX Gain b5-b0 RX Gain MSB b7-b6 Table 10. Detailed Register Map: AFE Control Byte 2 Title: AFE Control 2 (Tx PGA Gain) ...
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... CK35M is sent directly to PFD (vco input). 00 normal operation 01 Output of DIV69 counter is output to DIGREF pin 10 Output of DIV2/3/4/8 counter is output to DIGREF pin 11 Output of DIV5 counter is output to DIGREF pin STLC1511 Access Type: R/W Bits Used: 3 Reset 1 0 Access Type: R/W Bits Used: 5 Reset ...
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... STLC1511 Table 13. Detailed Register Map: AFE Control 5 Title: AFE Control 5 (PLL Control) Label: PLL Control Address: 100 Description: PLL Control Register Bit Label Bit(s) Clock Source Control b0- OSC Mode PLL Mode b3 2 b5-b4 FREF Mode DIGREF Enable b6 reserved b7 <1>Presently there is no difference in the oscillator driver between CO Oscillator and CPE modes so this bit is unused. However, it may be required in the future and should be programmed correctly in case needed. < ...
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... AFE Read only Status Bit Label Bit(s) Clip Status? b0 not used b7-b2 Value Bit Description Value Bit Description Value Bit Description 0 A/D clip not detected 1 A/D clip detected STLC1511 Access Type: R/W Bits Used: 0 Reset 00000000 Access Type: R/W Bits Used: 0 Reset 00000000 Access Type: R Bits Used: 2 ...
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... STLC1511 3.8 TIMING Table 17. describes the timing relationships between important signals. Table 17. Timing Symbol t ENB falling to DIGCLK rising SENB t ENB rising to DIGCLK falling HENB t Data in valid to DIGCLK falling SDRX t DIGCLK falling to Data in hold HDRX t DIGCLK rising to Data out valid DDTX t TXSIN[1:0] valid to CK35M falling ...
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... Table 21. defines the maximum and minimum power supply requirements to meet specifications as outlined in section 3.2 and 3.3. Table 21. Power Supply Limits Parameter Positive Supply Voltage 6 layer, 1oz copper natural convection 300mW 6 layer, 1oz copper natural convection 300mW 0 - -40 to +85 C Limits Unit 1 min typ max 4.75 5 5.25 Volts STLC1511 Conditions 27/31 ...
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... STLC1511 Table 21. Power Supply Limits Parameter Tx Powered Up CO Oscillator mode CO External Clock mode CPE mode Tx Powered Down CO Oscillator mode CO External Clock mode CPE mode Tx Powered up CO Oscillator mode CO External Clock mode CPE mode Tx Powered Down CO Oscillator mode CO External Clock mode CPE mode < ...
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... Low level output voltage Voh High level output voltage <1>Characterized for VCC=3.0 to 3.6V. This pad must be characterized at VCC=5.0V+-5% and the table updated <2>Assumes a 200mV voltage drop in both supply lines. This will not be the case in the STLC1511. Table 26. TTL Input Pad (TLCHT) DC Electrical Characteristics Parameter Vil ...
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... STLC1511 4.7 Package The STLC1511 will be packaged in a 64pin 10x10x1.4mm Thin Quad Flat Pack (TQFP) package. mm DIM. MIN. TYP. MAX. MIN. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.18 0.23 0.28 0.007 C 0.12 0.16 0.20 0.0047 0.0063 0.0079 D 12.00 D1 10.00 D3 7.50 e 0.50 E 12.00 E1 10.00 E3 7.50 L 0.40 0.60 0.75 0.0157 0.0236 0.0295 L1 1.00 K (min.), 7 (max 30/31 inch TYP ...
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