cs5331a Cirrus Logic, Inc., cs5331a Datasheet
cs5331a
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... C) on page 16 LP Filter Digital Decimation Comparator DAC Digital Decimation LP Filter Comparator DAC Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) CS5330A/31A Automotive grades -10° to +70° C) and . Please refer to “Ordering Information” for complete details. MCLK SCLK ...
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... ORDERING INFORMATION ................................................................................................. 16 8. REVISION HISTORY .............................................................................................................. 16 LIST OF FIGURES Figure 1. Typical Connection Diagram......................................................................................... 8 Figure 2. Data Output Timing-CS5330A .................................................................................... 10 Figure 3. Data Output Timing - CS5331A (I²S Compatible) ....................................................... 10 Figure 4. CS5330A/31A Initialization and Power-Down Sequence............................................ 12 Figure 5. CS5330A/31A Digital Filter Stopband Rejection......................................................... 13 Figure 6. CS5330A/31A Digital Filter Transition Band ............................................................... 13 Figure 7. ...
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PIN DESCRIPTIONS SERIAL DATA OUTPUT SERIAL DATA CLOCK LEFT/RIGHT CLOCK MASTER CLOCK Pin Name # Pin Description Audio Serial Data Output (Output) - Two’s complement MSB-first serial data is output on this SDATA 1 pin kΩ resistor ...
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CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25°C.) A SPECIFIED OPERATING CONDITIONS (AGND = ...
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ANALOG INPUT CHARACTERISTICS (-1 dBFS Input Sinewave, 997 Hz; Measurement Bandwidth kHz unless otherwise specified; Logic 0 = 0V, Logic 1 = VD+) Parameter Dynamic Performance Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise ...
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DIGITAL CHARACTERISTICS Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage -20 µA Low-Level Output Voltage µA Input leakage Current DIGITAL FILTER CHARACTERISTICS ( kHz) Parameter Passband Passband Ripple Stopband ...
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SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0V, Logic 1 = VA+; C Parameter Output Sample Rate MCLK Period MCLK Low MCLK High MCLK Period MCLK Low MCLK High MCLK Period MCLK Low MCLK High MASTER MODE SCLK falling to LRCK ...
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... SCLK to SDATA LRCK - MASTER mode (CS5331A sclkl sclkh SCLK input (SLAVE mode) t sclkw LRCK input (SLAVE mode) t dss MSB-1 MSB-2 SDATA SCLK to LRCK & SDATA - SLAVE mode (CS5331A) 0.1 µ VA+ 8 AINL MCLK CS5330A CS5331A SCLK 5 LRCK AINR SDATA AGND 6 Figure 1 ...
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... In Master mode, SCLK and LRCK are outputs which are internally derived from MCLK. The CS5330A/31A will divide MCLK generate a SCLK which is 64× Fs and by 256 to generate LRCK. The CS5330A and CS5331A can be placed in the Master mode with a 47 kohm pull-down resistor on the SDATA pin as shown in Figure 1. ...
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... LRCK transitions and the MSB of the data. The falling edges of SCLK cause the ADC to output the eigh- teen data bits. The data bits are valid during the rising edge of SCLK. LRCK is also inverted compared to the CS5330A interface. The CS5331A interface is compatible with I LRCK ...
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Analog Connections Figure 1 shows the analog input connections. The analog inputs are presented to the modula-tors via the AINR and AINL pins. Each analog input will accept a maximum of 4 Vpp centered at +2.4 V. The CS5330A/31A ...
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... Figure 4. CS5330A/31A Initialization and Power-Down Sequence The CS5330A and CS5331A have a Power-Down mode wherein typical consumption drops to 0.5 mW. This is initiated when a loss of clock is detected on either the LRCK or MCLK pins in Slave Mode, or the MCLK pin in Master Mode. The initialization sequence will begin when MCLK, and LRCK for slave mode, are restored ...
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Digital Filter Figures 5 through 8 show the attenuation characteristics of the digital filter included in the ADC. The filter response scales linearly with sample rate. The x-axis has been normalized to Fs, and can be scaled by multiplying ...
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PARAMETER DEFINITIONS Resolution The total number of possible output codes is equal where N = the number of bits in the output word for each channel. Dynamic Range The ratio of the full-scale rms value of ...
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REFERENCES 1. Area Efficient Decimation Filter for an 18-Bit Delta- Sigma ADC Lin and J.J. Paulos. Paper presented at the 98th Convention of the Audio Engineering Society, February 1995 18-Bit, 8-Pin Stereo Digital-to-Analog Converter, by ...
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... CS5330A/31A Container Order # Bulk CS5330A-KS Tape & Reel CS5330A-KSR Bulk CS5331A-KS Tape & Reel CS5331A-KSR Bulk CS5330A-KSZ Tape & Reel CS5330A-KSZR Bulk CS5331A-KSZ Tape & Reel CS5331A-KSZR Bulk CS5330A-BS Tape & Reel CS5330A-BSR Bulk CS5331A-DSZ Tape & Reel CS5331A-DSZR DS138F5 ...