cs5371 Cirrus Logic, Inc., cs5371 Datasheet - Page 17

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cs5371

Manufacturer Part Number
cs5371
Description
Low-power, High-performance ?? Modulators
Manufacturer
Cirrus Logic, Inc.
Datasheet

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ST
0
INF-
VREF+
VREF-
Digital Inputs
MCLK
MSYNC
OFST
LPWR
PWDN
Digital Outputs
MDATA
MFLAG
DS255F3
_
Fine inverting analog input.
Input for an external +2.5 V voltage reference relative to VREF-.
This pin should be tied to VA-.
A CMOS compatible clock input for the modulator internal master clock, nominally 2.048 MHz
with an amplitude equal to the VD digital power supply.
A low to high transition resets the internal clock phasing of the modulator. This assures the
sampling instant and modulator data output are synchronous to the external system.
_
When high, adds approximately -50 mV of offset to the analog inputs to guarantee any ∆Σ idle
tones are removed. When low, no offset is added.
When set high with MCLK operating at 1.024 MHz, modulator power dissipation is reduced to
15 mW per channel.
When high, the modulator is in power-down mode and consumes 1 mW. Halting MCLK while
in power down mode reduces modulator power dissipation to 10
Modulator data is output as a 1-bit serial data stream at 512 kHz with an MCLK input of
2.048 MHz. Modulator data is output at 256 kHz with an MCLK input of 1.024 MHz.
A high level output indicates the modulator is unstable due to an over-range on the analog
inputs.
Fine Inverting Input, pin 3
_
_
_
_
_
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Offset Mode Select, pin 14
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_
Modulator Clock Input, pin 19
Low Power Mode Select, pin 23
Negative Voltage Reference Input, pin 6
Power-down Mode, pin 24
Positive Voltage Reference Input, pin 5
Modulator Data Output, pin 21
Modulator Flag Output, pin 22
Modulator Sync Input, pin 20
µW
.
CS5371 CS5372
17

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