adc1220 austriamicrosystems, adc1220 Datasheet

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adc1220

Manufacturer Part Number
adc1220
Description
Cmos 12-bit Pipelined A/d Converter
Manufacturer
austriamicrosystems
Datasheet
ANALOG IP BLOCK
ADC1220 - CMOS 12-Bit Pipelined A/D CONVERTER
PROCESS
C35B3 (0.35um)
Revision B, 08.09.02
FEATURES
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Small Area: 3.87 mm
Size x = 2261.5 µm y = 1711.55 µm
Supply Voltage 3.0 - 3.6 V
Junction Temp. Range: −40 to +125 °C
Resolution 12-Bit
Maximum Sampling Rate 20 MS/s
Sample and Hold Input Stage
2 Vpp or 3 Vpp Input Signal Range
Fully Differential Input
Power Dissipation 380 mW
Power Down Mode
EN8, EN16
VBYSHN
VBYSHP
ONADC
ONREF
CTRSH
SWIB
LWJIT
CLKIN
VINP
VINN
VCM
VBG
2
GEN.
REF.
VDDA
GNDA
S/H
Bias Current Generation
GNDA2
VDDA2
Pipeline
SGNDA
SVDDA
ADC
Timing Generation
DESCRIPTION
The ADC1220 is a high-speed pipeline ADC core cell
achieving sampling rates up to 20 MS/s. A S/H circuit is
built-in to provide low jitter noise and a fully differential
input. The reference voltages are internally generated
from a bandgap reference that must be supplied to the
cell or must be supplied externally to the cell. A power
down capability is included for very low power
dissipation in stand-by mode.
SGNDD
SVDDD
Digital Error
Correction
VDDD2
GNDD2
Register
VDDD
Output
GNDD
B11
B0
IB_EXT
VREFN
VREFP
CLKOUT
Page 1 of 12
DATA SHEET

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adc1220 Summary of contents

Page 1

... LWJIT CLKIN GNDA Revision B, 08.09.02 DESCRIPTION The ADC1220 is a high-speed pipeline ADC core cell achieving sampling rates MS/s. A S/H circuit is built-in to provide low jitter noise and a fully differential input. The reference voltages are internally generated from a bandgap reference that must be supplied to the cell or must be supplied externally to the cell ...

Page 2

... Max. Input Signal Frequency inmax 1) For 2 Vpp input signal range. 2) For 3 Vpp input signal range. 3) VBG = 1.25 V and VDDA = 3 VBG = 1.875 V and VDDA = 3 strongly recommended not to overdrive the inputs of the ADC1220. Revision B, 08.09.02 Conditions Min Typ 12 12 –0.9 ±0.5 –2.0 ±0.5 – ...

Page 3

... Datasheet : ADC1220 – C35 AC ACCURACY (2 Vpp input signal range) Symbol Parameter THD Total Harmonic Distortion THD Total Harmonic Distortion THD Total Harmonic Distortion SFDR Spurious Free Dynamic Range SFDR Spurious Free Dynamic Range SFDR Spurious Free Dynamic Range SNR Signal to Noise Ratio ...

Page 4

... Datasheet : ADC1220 – C35 DIGITAL INPUTS AND OUTPUTS Symbol Parameter VDD Pos. digital Supply Voltage VSS Neg. digital Supply Voltage VIL Digital Input Level VIH VOL Digital Output Level VOH B[11:0] Output Code POWER REQUIREMENTS Symbol Parameter VDDA Pos. analog Supply Voltage VSSA Neg ...

Page 5

... Datasheet : ADC1220 – C35 TYPICAL PERFORMANCE CHARACTERISTICS ( °C, VDDA = VDD = +3.3 V, fclk = 20 MHz, VBG = 1.25 V, VCM = VDDA/2, Op. Mode 1, unless otherwise specified) DNL @ 180 kHz Input Signal Frequency [Hz] Spectrum @ 180 kHz Input Signal Frequency [Hz] Two-Tone IMD @ 4.0 MHz and 4.5 MHz 1) The spectrum consists of 16384 pins. ...

Page 6

... Datasheet : ADC1220 – C35 SYMBOL THEORY OF OPERATION The ADC1220 is a low-power 12-bit ADC capable of sampling at 20 MS/s. It uses a fully differential pipelined architecture with a first 3.5-bit stage, followed by seven 1.5-bit per stage and digital error correction to achieve improved linearity performance. A dedicated wide-band input sample- ...

Page 7

... Datasheet : ADC1220 – C35 OPERATING MODES The modes of operation are summarized in the table bellow, and described in detail as follows. Mode Objective 0 Complete Power Down 1 Normal conversion 2 Normal conversion with external VREF 3 Normal conversion with external Ibias 4 Normal conversion with external VREF and Ibias ...

Page 8

... CONVERSION MODE Fully Differential Mode It is recommended to use the ADC1220 as a Fully Differential Converter. Both inputs VINP and VINN should be balanced around VCM. CODE TABLES The digital representation of the data bus in both conversion modes is described in the following table. ...

Page 9

... TIMING DIAGRAM OF ADC1220 The sampling rate of the ADC1220 is defined by the frequency of the CLK signal. The input signal voltage of the ADC is sampled in the falling edge of CLK. As the conversion stages operate in a staggered fashion in alternate phases of CLK, the duty-cycle of this signal must be 50%. The results are latched in the output register on the falling edge of CLK, with a latency of 5 CLK periods ...

Page 10

... Datasheet : ADC1220 – C35 The Diagram 2 presents the timing of the CLKOUT signal in normal operation (mode 0) and with decimation factors of 8 (mode 5) and 16 (mode 6). In all test modes that do not have a decimation factor specified, the CLKOUT signal is identical to that in normal operation mode. ...

Page 11

... Datasheet : ADC1220 – C35 TYPICAL APPLICATION The ADC1220 is targeted for general purpose sampling ADC functions where high-speed conversion rates and medium precision are of critical importance CPK1 10uF 100nF 100pF 2) 2) CPK2 3.3uF 100nF 100pF Configuration: Op. Mode MS/sec, 2 Vpp input signal range ...

Page 12

... Datasheet : ADC1220 – C35 Contact austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 support@austriamicrosystems.com Revision B, 08.09.02 Copyright Copyright © 2002 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner ...

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