ad1882a Analog Devices, Inc., ad1882a Datasheet
ad1882a
Available stocks
Related parts for ad1882a
ad1882a Summary of contents
Page 1
... V analog and digital supply voltage 1.5 V and 3 Audio link signaling Very low power consumption in D3 state S/PDIF OUT DIGITAL BEEP DM_CLK DM_DATA Figure 1. AD1882A Block Diagram One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 High Definition Audio SoundMAX Codec AD1882A ® ...
Page 2
... AD1882A CONTENTS Features ................................................................. 1 Contents ................................................................ 2 Revision History ...................................................... 2 General Description ................................................. 3 Special Software Features ........................................ 3 Additional Information .......................................... 3 Jack Configuration ................................................ 3 Specifications .......................................................... 4 Test Conditions .................................................... 4 Performance ........................................................ 4 General Specifications ............................................ 4 HD Audio Link Specifications .................................. 6 Power-Down States ............................................... 6 Absolute Maximum Ratings .................................... 7 ESD Caution ........................................................ 7 Environmental Conditions ...................................... 7 Pin Configuration and Function Descriptions ................. 8 Digital Microphone Interface Timing Specifications ....... 11 HD Audio Parameters ...
Page 3
... The AD1882A audio codec and SoundMAX superior HD audio quality that exceeds Vista Premium perfor- mance. The AD1882A has six DACs and four ADCs, two stereo headphone ports, C/LFE swapping, digital and analog PCBeep, and S/PDIF output, making the AD1882A the right choice for desktop and notebook PCs where performance is the primary consideration ...
Page 4
... AD1882A SPECIFICATIONS TEST CONDITIONS Parameter Test Condition Temperature 25°C Digital Supply 3.3 V Analog Supply 3.3 V MIC_BIAS_IN (via Low-Pass Filter) 5.0 V Sample Rate f 48 kHz S Input Signal (Frequency Sine Wave) 1008 Hz Amplitude for THD + N –3.0 dB Full Scale Analog Output Pass Band kHz DAC 10 kΩ ...
Page 5
... External Load Capacitance Boost = 0 dB Boost = 10 dB Boost = 20 dB Boost = –500 μA I OUT = +1500 μA I OUT = –500 μA I OUT = +1500 μA I OUT Rev Page August 2008 AD1882A Min Typ Max 24 ±10 ±0.5 –95 1.5 –58.5 0 –80 1.5 –58.5 +22.5 –80 95 1.5 –34.5 +12.0 1.0 2.83 300 ...
Page 6
... AD1882A Parameter DM_DATA Input Signal High ( Input Signal Low ( Input Leakage Current (Signal High) (I Input Leakage Current (Signal Low S/PDIF_OUT Output Signal High ( Output Signal Low ( POWER SUPPLY Analog (AV ) 3.3 V ± Power Supply Range Power Dissipation Supply Current ) 3.3 V ± ...
Page 7
... CA θ = thermal resistance (junction-to-ambient) JA θ = thermal resistance (junction-to-case) JC All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7. Package LFCSP_VQ + 0 0 Rev Page August 2008 AD1882A ) CA θ θ θ Unit °C ...
Page 8
... RESET 11 12 PCBEEP AD1882AJCPZ TOP VIEW (Not To Scale Figure 2. AD1882A 48-Lead Package and Pinout Rev Page August 2008 PORT-D_R 36 PORT-D_L 35 SENSE_B/SRC_A 34 33 MIC_BIAS_IN 32 RESERVED (NC) MIC_BIAS RESERVED (NC) 29 MIC_BIAS-C 28 MIC_BIAS-B 27 VREF_FLT ...
Page 9
... Link Serial Data Output. AD1882A input stream. Clocked on both edges of the BIT_CLK. Link Bit Clock. 24.000 MHz serial data clock. Link Serial Data Input. AD1882A output stream clocked only on one edge of BIT_CLK. Link Frame Sync. Link Reset. AD1882A master hardware reset General-Purpose Input/Output ...
Page 10
... Source Power for Microphone Bias Circuitry. Connect this pin to 5.0 V via a low-pass filter. When connected this way, the AD1882A is capable of providing 3 mic bias to all of the MIC_BIAS pins not available, connect this pin to 3.3 V (AV via a low-pass filter. ...
Page 11
... Min 100 Figure 3. Uniplex Microphone Timing RIGHT DATA VALID LEFT DATA VALID Figure 4. Multiplex Microphone Timing Rev Page August 2008 AD1882A Figure 3 and Figure 4. The interface Typ Max 667 50/50 500 50/50 333 50/ ...
Page 12
... AD1882A HD AUDIO PARAMETERS The SSID value is set on codec power-up only. SSID is not reset by link or soft reset in order to preserve modifications by BIOS control. Table 8. Root and Function Node Parameters Vendor ID Node ID Name 00 00 ROOT 11D4882A 01 FUNCTION 1 Subject to change with silicon stepping. 1 Table 9. SubSystem ID ...
Page 13
... Rev Page August 2008 AD1882A ConnList Output Amp Length Power States Capabilities 0x0000 0009 0x0005 2727 0x0000 0001 ...
Page 14
... AD1882A HD AUDIO WIDGETS In the following table, node IDs that are not shown are reserved for future use. Table 11. HD Audio Widgets Node ID Name Type ID 00 ROOT x 01 FUNCTION x 02 S/PDIF DAC 0 03 DAC_0 0 04 DAC_1 0 05 DAC_2 0 08 ADC_0 1 09 ADC_1 ...
Page 15
... Rev Page August 2008 AD1882A NID I NID I NID I 0x1F 0x3B 0x12 0x1F 0x3B 10x2 0x3C 0x3B 0x18 0x24 ...
Page 16
... AD1882A DEFAULT CONFIGURATION BYTES In Table 13, default configuration values are set on codec power-up only. Default configuration values are not reset by link or soft reset to preserve modifications by BIOS control. Table 13. Default Configuration Bytes 31:30 Name Value Connectivity Port A (Headphone) 0x0221 401F Jack Port D (Front L/R) 0x0101 4010 Jack ...
Page 17
... Figure 5. 48-Lead, Lead Frame Chip Scale Package [LFCSP_VQ Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters Package Description 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ, 13” Tape and Reel Rev Page August 2008 0.30 0.23 0.18 PIN 1 INDICATOR EXPOSED 5.25 PAD 5.10 SQ (BOTTOM VIEW) 4. 0.25 MIN 5.50 REF Package Option CP-48-1 CP-48-1 AD1882A ...
Page 18
... AD1882A Rev Page August 2008 ...
Page 19
... Rev Page August 2008 AD1882A ...
Page 20
... AD1882A ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07549-0-8/08(0) Rev Page August 2008 ...