ad1870arz-reel Analog Devices, Inc., ad1870arz-reel Datasheet - Page 11

• Manufacturer Part Number: ad1870arz-reel
• Description: Single-supply 16-bit Stereo Adc
• Manufacturer: Analog Devices, Inc.

REV. A
S/M RLJUST
1
1
1
1
0
0
0
0
Figure 5 shows a circuit for obtaining a 3 dB improvement in
dynamic range by using both channels of a single AD1870 with a
mono input. A stereo implementation would require using
two AD1870s and using the recommended input structure
shown in Figure 2. Note that a single microprocessor would likely
be able to handle the averaging requirements for both left and
right channels.
CHANNEL
SINGLE
INPUT
Figure 5. Increasing Dynamic Range By Using Two
AD1870 Channels
1
1
0
0
1
1
0
0
RECOMMENDED
INPUT BUFFER
AD1870
MSBDLY
1
0
1
0
1
0
1
0
V
AD1870
V
IN
IN
R
L
WCLK
Output
Input
Output
Output
Output
Output
Output
Output
AVERAGER
DIGITAL
Input
Input
Input
Input
Output
Output
Output
Output
BCLK
SINGLE
CHANNEL
OUTPUT
LRCK
Input
Input
Input
Input
Output
Output
Output
Output
–11–
Slave Mode. WCLK frames the data. The MSB is output on the
Slave Mode. The MSB is output in the BCLK cycle after
Slave Mode. Data left-justified with WCLK framing the data.
Slave Mode. Data I
Master Mode. Data right-justified. WCLK frames the data,
Master Mode. Data right-justified + 1. WCLK is pulsed in the
Master Mode. Data left-justified. WCLK frames the data.
Master Mode. Data I
Serial Port Operation Mode
17th BCLK cycle. Provides right-justified data in slave mode
with a 64 × f
WCLK is detected HI. WCLK is sampled on the BCLK active
edge, with the MSB valid on the next BCLK active edge. Tying
WCLK HI results in I
WCLK rises immediately after an LRCK transition. The MSB is
valid on the first BCLK active edge. See Figure 9.
WCLK rises in the second BCLK cycle after an LRCK transi-
tion. The MSB is valid on the second BCLK active edge. See
Figure 10.
going HI in the 17th BCLK cycle. BCLK frequency = 64 × f
See Figure 11.
17th BCLK cycle, staying HI for only 1 BCLK cycle. BCLK
frequency = 64 × f
BCLK frequency = 64 × f
BCLK frequency = 64 × f
DIGITAL INTERFACE
Modes of Operation
The AD1870’s flexible serial output port produces data in
two’s-complement, MSB-first format. The input and output
signals are TTL logic-level compatible. Time multiplexed serial
data is output on SOUT (Pin 26), left channel then right chan-
nel, as determined by the left/right clock signal LRCK (Pin 1).
Note that there is no method for forcing the right channel to
precede the left channel. The port is configured by pin selections.
The AD1870 can operate in either Master or Slave Mode, with
the data in right-justified, I
or left-justified positions.
The various mode options are pin programmed with the S/M
(Slave/Master) Pin (7), the Right/Left Justify Pin (21), and the
MSBDLY Pin (22). The function of these pins is summarized
below.
S
BCLK frequency. See Figure 7.
S
. See Figure 12.
2
S-justified with WCLK framing the data.
2
2
S-justified. WCLK frames the data.
S-justified data. See Figure 8.
S
S
2
. See Figure 13.
. See Figure 14.
S compatible, word clock controlled,
AD1870
S
.