pca9535ecmttxg ON Semiconductor, pca9535ecmttxg Datasheet - Page 12

• Manufacturer Part Number: pca9535ecmttxg
• Description: Pca9535e, Pca9535ec 16-bit Low-power I/o Expander For I2c Bus With Interrupt
• Manufacturer: ON Semiconductor

SCL
SDA
read from port 0
data into port 0
read from port 1
data into port 1
INT
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
SDA
read from port 0
data into port 0
read from port 1
data into port 1
SCL
INT
SDA
(cont.)
START condition
START condition
S A6
S A6
Remark: Transfer can be stopped at any time by a STOP condition.
S
1
1
START condition
t
t
A5 A4 A3
S
v(INT_N)
2
2
A5A4 A3
(repeated)
START condition
v(INT_N)
A6
slave address
slave address
3
3
A6
A5 A4 A3
4
4
slave address
A5 A4 A3
A2 A1 A0 1 A
5
A2 A1 A0 1 A
5
acknowledge
acknowledge
slave address
6
from slave
6
from slave
DATA 00
7
7
R/W
A2 A1 A0
R/W
8
8
A2 A1 A0
9
9
acknowledge
D
A
7
from slave
acknowledge
T
A
t
t
6 5 4 3 2 1 0
from slave
rst(INT_N)
0 1
rst(INT_N)
R/W
t
Figure 10. Read from Input Port Register, Scenario 2
h(D)
Figure 9. Read from Input Port Register, Scenario 1
0
R/W
D
1
A
I0.x
I0.x
A
T
A
DATA 01
acknowledge
acknowledge
0 0
A
from master
from master
MSB
Figure 8. Read from Register
COMMAND BYTE
upper byte of register
data from lower or
at this moment master−transmitter becomes master−receiver
and slave−receiver becomes slave−transmitter
DATA (first byte)
A
A
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7
6 5 4 3 2 1 0
t
h(D)
D
DATA 02
acknowledge
A
I1.x
I1.x
T
12
from slave
A
acknowledge
acknowledge
0 1
from master
from master
t
su(D)
LSB
D
A
A
T
A
A
A
A
acknowledge
from master
A
A
(cont.)
1 1
7
6 5 4 3 2 1 0
MSB
D
DATA 03
A
I0.x
I0.x
T
lower byte of register
A
data from upper or
acknowledge
acknowledge
3 0
DATA (last byte)
from master
from master
t
su(D)
no acknowledge
A
A
7
from master
6 5 4 3 2 1 0
LSB
D
A
D
I1.x
I1.x
T
A
non acknowledge
A
NA
T
non acknowledge
A
2 1
2 1
from master
from master
P
STOP condition
STOP condition
STOP
condition
1
1
P
P