pca9655e ON Semiconductor, pca9655e Datasheet - Page 10

• Manufacturer Part Number: pca9655e
• Description: Pca9655e Remote 16-bit I/o Expander For I2c Bus With Interrupt
• Manufacturer: ON Semiconductor

Registers 4 and 5: Polarity Inversion Registers
port registers to be inverted. The input port data polarity will
Registers 6 and 7: Configuration Registers
configuration registers. When a bit in the configuration
registers is set (written with ‘1’), the bit’s corresponding port
pin is enabled as an input with the output driver in
Power−on Reset
(POR) holds the PCA9655E in a reset condition while V
is ramping up. When V
condition is released and the PCA9655E registers and
SMBus state machine will initialize to their default states.
The reset is typically completed by the POR and the part
enabled by the time the power supply is above V
However, when doing a power reset cycle, it is necessary to
lower the power supply below 0.2 V, and then restored to the
operating voltage.
Table 12. POLARITY INVERSION PORT 0 REGISTER
Symbol
Default
Table 13. POLARITY INVERSION PORT 1 REGISTER
Symbol
Default
Table 14. CONFIGURATION PORT 0 REGISTER
Symbol
Default
Table 15. CONFIGURATION PORT 1 REGISTER
Symbol
Default
These registers allow the polarity of the data in the input
The I/O pin directions are configured through the
Upon application of power, an internal Power−On Reset
Bit
Bit
Bit
Bit
N0.7
N1.7
C0.7
C1.7
7
0
7
0
7
1
7
1
DD
has reached V
N0.6
N1.6
C0.6
C1.6
6
0
6
0
6
1
6
1
POR
N0.5
N1.5
C0.5
C1.5
, the reset
5
0
5
0
5
1
5
1
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POR
DD
.
10
N0.4
N1.4
C0.4
C1.4
4
0
4
0
4
1
4
1
be inverted when its corresponding bit in these registers is
set (written with ‘1’), and retained when the bit is cleared
(written with a ‘0’).
high−impedance. When a bit is cleared (written with ‘0’),
the corresponding port pin is enabled as an output. Note that
there is a high value resistor tied to V
the device’s ports are inputs with a pull−up to V
I/O Port (see Figure 2)
Q2 are off, creating a high−impedance input with a weak
pull−up (100 kW typ) to V
raised above V
or Q2 is enabled, depending on the state of the Output Port
register. Care should be exercised if an external voltage is
applied to an I/O configured as an output because of the
low−impedance path that exists between the pin and either
V
DD
When an I/O pin is configured as an input, FETs Q1 and
When the I/O pin is configured as an output, then either Q1
or V
N0.3
N1.3
C0.3
C1.3
SS
3
0
3
0
3
1
3
1
.
DD
to a maximum of 5.5 V.
N0.2
N1.2
C0.2
C1.2
2
0
2
0
2
1
2
1
DD
. The input voltage may be
DD
N0.1
N1.1
C0.1
C1.1
1
0
1
0
1
1
1
1
at each pin. At reset,
DD
N0.0
N1.0
C0.0
C1.0
.
0
0
0
0
0
1
0
1