tda9112a STMicroelectronics, tda9112a Datasheet - Page 37

• Manufacturer Part Number: tda9112a
• Description: High-end I2c Controlled Deflection Processor For Multisync Monitor
• Manufacturer: STMicroelectronics

9.3.4
The goal of the PLL2 is, by means of phasing the
signal driving the power deflection transistor, to
lock the middle of the horizontal flyback to a cer-
tain threshold of the VCO sawtooth. This internal
threshold is affected by geometry phase correc-
tions, like e.g., parallelogram. The PLL2 is fast
enough to be able to follow the dynamism of phase
modulation, this speed is strongly related to the
value of the capacitor on
trol current (see
during discharge of vertical oscillator (during verti-
cal retrace period) to be able to make up for the
difference of dynamic phase at the bottom and at
the top of the picture. The PLL2 control current is
integrated on the external filter on pin
obtain smoothed voltage, used, in comparison
with VCO ramp, as a threshold for H-drive rising
edge generation.
As both leading and trailing edges of the H-drive
signal in the
of the VCO ramp, an optimum middle position of
the threshold has been found to provide enough
margin for horizontal output transistor storage time
as well as for the trailing edge of H-drive signal
with maximum duty cycle. Yet, the constraints
thereof must be taken into account while consider-
ing the application frequency range and H-flyback
duration. The
and falling edges of the H-drive signal on
As it is forced high during the H-flyback pulse and
low during the VCO discharge period, no edge
during these two events takes effect.
The flyback input configuration is in
9.3.5
The dynamic phase control of PLL2 is used to
compensate for picture asymmetry versus vertical
axis across the middle of the picture. It is done by
modulating the phase of the horizontal deflection
with respect to the incoming video (synchroniza-
tion). Inside the device, the threshold
pared with the VCO ramp, the PLL2 locking the
middle of H-flyback to the moment of their match.
The dynamic phase is obtained by modulation of
the threshold by correction waveforms. Refer to
Figure 14
waveforms have no effect in vertical middle of the
screen (for middle vertical position). As they are
summed, their effect on the phase tends to reach
maximum span at top and bottom of the picture.
As all the components of the resulting correction
waveform (linear for parallelogram correction, pa-
PLL2
Dynamic PLL2 phase control
and
Figure 7
Figure 7
Chapter 7 - page 22
Figure 7
must fall inside the rising part
also shows regions for rising
) is significantly increased
HPLL2C
. The correction
. The PLL2 con-
Figure 8
VS(0)
HPLL2C
HOut
is com-
.
pin.
to
rabola of 2nd order for Pin cushion asymmetry cor-
rection and half-parabolas of 4th order for corner
corrections independently at the top and at the
bottom) are generated from the output vertical de-
flection drive waveform, they all track with real ver-
tical amplitude and position, thus being fixed on
the screen. Refer to
on I²C-bus controls.
Figure 7. Horizontal timing diagram
Figure 8.
(polarized)
(internal)
(on HOut)
H-fly-back
H-drive
H-drive
control
control
current
t
H-drive
H-sync
H-Osc
(VCO)
REF1
S
PLL2
region
region
: HOT storage time
PLL1 lock
HFly
HFly
VHPosF
ext.
max.
med.
min.
ON
12
tph(max)
input configuration
int.
min max
tHph
t
S
Chapter 8 - page 27
~20k
~500
+
tHoff
-
inhibited
GND
7/8T
VS(0)
forced high
OFF
VThrHFly
T
H
H
ON
VHOThrHi
forced low
TDA9112A
HPOS
VHOThrLo
(I²C)
for details
max.
med.
min.
37/60