as8510 austriamicrosystems, as8510 Datasheet - Page 38

• Manufacturer Part Number: as8510
• Description: Data Acquisition Device For Battery Sensors
• Manufacturer: austriamicrosystems

AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.9.2 Initialization Sequence at Power ON
Figure 16. AS8510 Device Initialization Sequence at Power ON
Device initialization starts if the DVDD and AVDD supplies are switched ON and DVDD > V
500µsec, and, during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization
should be ignored in the system. Device configuration and activation should be carried out only after the initialization period.
On ADC start, device enters into analog stabilization state and takes 1.5msec for oscillator and Reference to settle. After this 1.5msec period, the
first interrupt will occur after a time period of T
T
carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically
only when micro-controller reads this register. Data in the channel registers is changed after T
registers and status registers are not read during the T
Example:
Configuration registers are set as follows:
ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation
ratio of CIC2 = 4. With these settings the various time periods as shown in the
www.austriamicrosystems.com/AS8510
DATA
CLK_REG = 8’b0010_0000
DEC_REG_R1_I = 0100_0101
DEC_REG_R2_I = 1100_0101
FIR_CTL_REG_I = 0000_0100
T
(T
T
T
T
CHOP_CLK and POR_N are internal signals of the device.
ADC
DATA
DATA
DATA
DATA
CHOP_CLK
_
Channel Data
STATUS
POR_N
DVDD/AVDD
Register
= 1msec
_
_
_
V
_
PORHID
STATUS
INVALID
VALID
INT
STATUS
_
RD
/V
= T
_
PORHIA
= 8 µsec
is the time period during which the micro-controller should complete reading of data and status from the device. If reading is
_
RD
ADC
RD
= 100 µsec
= (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5)
- T
500µS
DATA
_
Configure
Device
INVALID
Start
ADC
1.5mS
= 1msec - 8 µsec
ADC
D1
.
DATA
T
0x0000
ADC
D2
_
INVALID
D3
duration.
Revision 3.4
D4
T
DATA_STATUS_RD
Figure 16
D1
DATA1
D2
T
DATA_VALID
are as follows:
PORHID
DATA
D3
. The duration period of Initialization is
_
VALID
D4
T
DATA_INVALID
duration. Ensure that data channel
D1
DATA2
D2
D3
D4
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