epm3064a Altera Corporation, epm3064a Datasheet - Page 32

• Manufacturer Part Number: epm3064a
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet
32
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
Symbol
CLR
PIA
LPA
Symbol
PD1
PD2
SU
H
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
Table 19. EPM3064A Internal Timing Parameters (Part 2 of 2)
Table 20. EPM3128A External Timing Parameters
Register clear time
PIA delay
Low–power adder
Input to non–
registered output
I/O input to non–
registered output
Global clock setup
time
Global clock hold time
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output
delay
Array clock high time
Array clock low time
Minimum pulse width
for clear and preset
Minimum global clock
period
Maximum internal
global clock frequency
Minimum array clock
period
Parameter
Parameter
C1 = 35 pF
(2)
C1 = 35 pF
(2)
(2)
(2)
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(3)
(2)
(2),
(2)
Conditions
(4)
(2)
(5)
Conditions
192.3
Min
3.3
0.0
1.0
2.0
2.0
1.8
0.2
1.0
2.0
2.0
2.0
–5
Note (1)
Min
Max
5.0
5.0
3.4
4.9
5.2
5.2
–4
Max
1.3
1.0
3.5
129.9
Speed Grade
Min
3.0
3.0
4.9
0.0
1.0
2.8
0.3
1.0
3.0
3.0
3.0
Note (1)
Speed Grade
Min
–7
–7
Max
7.5
7.5
5.0
7.1
7.7
7.7
Max
2.1
1.7
4.0
98.0
Min
6.6
0.0
1.0
4.0
4.0
3.8
0.4
1.0
4.0
4.0
4.0
Min
Altera Corporation
–10
–10
Max
Max
10.2
10.2
2.9
2.3
5.0
6.6
9.4
10
10
Unit
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns