xc95144-15tqg100i Xilinx Corp., xc95144-15tqg100i Datasheet
![no-image](/images/no-image-200.jpg)
xc95144-15tqg100i
Available stocks
Related parts for xc95144-15tqg100i
xc95144-15tqg100i Summary of contents
Page 1
... Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See ture overview. Power Management Power dissipation can be reduced in the XC95144 by con- figuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for ...
Page 2
... JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95144 Architecture www.xilinx.com 36 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells Function ...
Page 3
... mA Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz www.xilinx.com XC95144 In-System Programmable CPLD Value –0.5 to 7.0 –0 0.5 CC –0 0.5 CC –65 to +150 +150 Min Max o C 4.75 5. 4.5 5 4.75 5. 4.5 5.5 3.0 3 ...
Page 4
... XC95144 In-System Programmable CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO (1) f 16-bit counter frequency CNT (2) f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input ...
Page 5
... Time Adders (1) T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW Notes multiplied by the span of the function as defined in the XC9500 family data sheet. PTA DS067 (v5.6) April 3, 2006 Product Specification XC95144 In-System Programmable CPLD XC95144-7 XC95144-10 Min Max Min Max - 2.5 - 3.5 - 1 ...
Page 6
... XC95144 In-System Programmable CPLD XC95144 I/O Pins Function Macro- Block cell TQ100 PQ100 PQ160 1 1 – – – – – ...
Page 7
... XC95144 In-System Programmable CPLD Macro- cell TQ100 PQ100 PQ160 1 – – – – – – – ...
Page 8
... XC95144 In-System Programmable CPLD XC95144 Global, JTAG, and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS V 5V CCINT V 3.3V/5V CCIO GND 100, 21, 31, 44, 62, 69, 75, No Connects 8 TQ100 PQ100 ...
Page 9
... XC95144-15PQ100C 15 ns XC95144-15PQG100C 15 ns XC95144-15TQ100C 15 ns XC95144-15TQG100C 15 ns XC95144-15PQ160C 15 ns XC95144-15PQG160C 15 ns XC95144-15PQ100I 15 ns XC95144-15PQG100I 15 ns XC95144-15TQ100I 15 ns XC95144-15TQG100I 15 ns DS067 (v5.6) April 3, 2006 Product Specification R XC95xxx TQ144 Package 7C Speed 1 Sample package with part marking. Pkg. No. of Symbol Pins PQ100 100-pin Plastic Quad Flat Pack (PQFP) PQG100 100-pin Plastic Quad Flat Pack (PQFP) ...
Page 10
... XC95144 In-System Programmable CPLD Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC95144-15PQ160I 15 ns XC95144-15PQG160I 15 ns Notes Commercial 0° to +70° Industrial Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www ...