xc95144-15tqg100i Xilinx Corp., xc95144-15tqg100i Datasheet

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xc95144-15tqg100i

Manufacturer Part Number
xc95144-15tqg100i
Description
Xc95144 In-system Programmable Cpld
Manufacturer
Xilinx Corp.
Datasheet

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Part Number:
XC95144-15TQG100I
Manufacturer:
XILINX
0
DS067 (v5.6) April 3, 2006
Features
DS067 (v5.6) April 3, 2006
Product Specification
7.5 ns pin-to-pin logic delays on all pins
f
144 macrocells with 3,200 usable gates
Up to 133 user I/O pins
5V in-system programmable
-
-
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
-
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
CNT
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables,
set and reset signals
to 111 MHz
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
5
XC95144 In-System
Programmable CPLD
Product Specification
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See
ture overview.
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
Where:
Figure 1
device.
CC
(mA) = MC
Figure 1: Typical I
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
(300)
(160)
600
400
200
0
HP
LP
shows a typical calculation for the XC95144
= Macrocells in low-power mode
= Macrocells in high-performance mode
HP
(1.7) + MC
Clock Frequency (MHz)
CC
vs. Frequency for XC95144
LP
50
(0.9) + MC (0.006 mA/MHz) f
Figure 2
for the architec-
DS067_01_110101
100
(480)
(320)
1

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xc95144-15tqg100i Summary of contents

Page 1

... Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See ture overview. Power Management Power dissipation can be reduced in the XC95144 by con- figuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for ...

Page 2

... JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95144 Architecture www.xilinx.com 36 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells Function ...

Page 3

... mA Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz www.xilinx.com XC95144 In-System Programmable CPLD Value –0.5 to 7.0 –0 0.5 CC –0 0.5 CC –65 to +150 +150 Min Max o C 4.75 5. 4.5 5 4.75 5. 4.5 5.5 3.0 3 ...

Page 4

... XC95144 In-System Programmable CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO (1) f 16-bit counter frequency CNT (2) f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input ...

Page 5

... Time Adders (1) T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW Notes multiplied by the span of the function as defined in the XC9500 family data sheet. PTA DS067 (v5.6) April 3, 2006 Product Specification XC95144 In-System Programmable CPLD XC95144-7 XC95144-10 Min Max Min Max - 2.5 - 3.5 - 1 ...

Page 6

... XC95144 In-System Programmable CPLD XC95144 I/O Pins Function Macro- Block cell TQ100 PQ100 PQ160 1 1 – – – – – ...

Page 7

... XC95144 In-System Programmable CPLD Macro- cell TQ100 PQ100 PQ160 1 – – – – – – – ...

Page 8

... XC95144 In-System Programmable CPLD XC95144 Global, JTAG, and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS V 5V CCINT V 3.3V/5V CCIO GND 100, 21, 31, 44, 62, 69, 75, No Connects 8 TQ100 PQ100 ...

Page 9

... XC95144-15PQ100C 15 ns XC95144-15PQG100C 15 ns XC95144-15TQ100C 15 ns XC95144-15TQG100C 15 ns XC95144-15PQ160C 15 ns XC95144-15PQG160C 15 ns XC95144-15PQ100I 15 ns XC95144-15PQG100I 15 ns XC95144-15TQ100I 15 ns XC95144-15TQG100I 15 ns DS067 (v5.6) April 3, 2006 Product Specification R XC95xxx TQ144 Package 7C Speed 1 Sample package with part marking. Pkg. No. of Symbol Pins PQ100 100-pin Plastic Quad Flat Pack (PQFP) PQG100 100-pin Plastic Quad Flat Pack (PQFP) ...

Page 10

... XC95144 In-System Programmable CPLD Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC95144-15PQ160I 15 ns XC95144-15PQG160I 15 ns Notes Commercial 0° to +70° Industrial Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www ...

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