adsp-21020 Analog Devices, Inc., adsp-21020 Datasheet - Page 6

• Manufacturer Part Number: adsp-21020
• Description: 32/40-bit Ieee Floating-point Dsp Microprocessor
• Manufacturer: Analog Devices, Inc.

ADSP-21020
Pin
Name
DMPAGE O
DMTS
CLKIIN
RESET
IRQ
FLAG
BR
BG
TIMEXP
RCOMP
EVDD
EGND
3–0
3–0
Type Function
I/S
I
I/A
I/A
I/O/A External Flags. Each is configured via
I/A
O
O
P
G
Data Memory Page Boundary. The ADSP-
21020 asserts this pin to signal that a data
memory page boundary has been crossed.
Memory pages must be defined in the
memory control registers.
Data Memory Three-State Control. DMTS
places the data memory address, data,
selects, and strobes in a high-impedance
state. If DMTS is asserted while a DM
access is occurring, the processor will halt
and the memory access will not be
completed. DMACK must be asserted for
at least one cycle when DMTS is
deasserted to allow any pending memory
access to complete properly. DMTS should
only be asserted (low) during an active
memory access cycle.
External clock input to the ADSP-21020.
The instruction cycle rate is equal to
CLKIN. CLKIN may not be halted,
changed, or operated below the specified
frequency.
Sets the ADSP-21020 to a known state and
begins execution at the program memory
location specified by the hardware reset
vector (address). This input must be
asserted (low) at power-up.
Interrupt request lines; may be either edge
triggered or level-sensitive.
control bits as either an input or output. As
an input, it can be tested as a condition. As
an output, it can be used to signal external
peripherals.
Bus Request. Used by an external device to
request control of the memory interface.
When BR is asserted, the processor halts
execution after completion of the current
cycle, places all memory data, addresses,
selects, and strobes in a high-impedance
state, and asserts BG. The processor
continues normal operation when BR is
released.
Bus Grant. Acknowledges a bus request
(BR), indicating that the external device
may take control of the memory interface.
BG is asserted (held low) until BR is
released.
Timer Expired. Asserted for four cycles
when the value of TCOUNT is
decremented to zero.
Compensation Resistor input. Controls
compensated output buffers. Connect
RCOMP through a 1.8 k
to EVDD. Use of a capacitor (approxi-
mately 100 pF), placed in parallel with the
1.8 k resistor is recommended.
Power supply (for output drivers),
nominally +5 V dc (10 pins).
Power supply return (for output drivers);
(16 pins).
15% resistor
–6–
Pin
Name
IVDD
IGND
TCK
TMS
TDI
TDO
TRST
NC
INSTRUCTION SET SUMMARY
The ADSP-21020 instruction set provides a wide variety of
programming capabilities. Every instruction assembles into a
single word and can execute in a single processor cycle.
Multifunction instructions enable simultaneous multiplier and
ALU operations, as well as computations executed in parallel
with data transfers. The addressing power of the ADSP-21020
gives you flexibility in moving data both internally and
externally. The ADSP-21020 assembly language uses an
algebraic syntax for ease of coding and readability.
The instruction types are grouped into four categories:
The instruction types are numbered; there are 22 types. Some
instructions have more than one syntactical form; for example,
Instruction 4 has four distinct forms. The instruction number
itself has no bearing on programming, but corresponds to the
opcode recognized by the ADSP-21020 device.
Because of the width and orthogonality of the instruction word,
there are many possible instructions. For example, the ALU
supports 21 fixed-point operations and 24 floating-point
operations; each of these operations can be the compute portion
of an instruction.
The following pages provide an overview and summary of the
ADSP-21020 instruction set. For complete information, see the
ADSP-21020 User’s Manual. For additional reference informa-
tion, see the ADSP-21020 Programmer’s Quick Reference.
This section also contains several reference tables for using the
instruction set.
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•
•
•
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Table I describes the notation and abbreviations used.
Table II lists all condition and termination code mnemonics.
Table III lists all register mnemonics.
Tables IV through VII list the syntax for all compute
Table VIII lists interrupts and their vector addresses.
Compute and Move or Modify
Program Flow Control
Immediate Move
Miscellaneous
(ALU, multiplier, shifter or multifunction) operations.
Type
P
G
I
I/S
VS
O
I/A
Function
Power supply (for internal circuitry),
nominally +5 V dc (4 pins).
Power supply return (for internal circuitry); (7
pins).
Test Clock. Provides an asynchronous clock
for JTAG boundary scan.
Test Mode Select. Used to control the test
state machine. TMS has a 20 k internal
pullup resistor.
Test Data Input. Provides serial data for the
boundary scan logic. TDI has a 20 k internal
pullup resistor.
Test Data Output. Serial scan output of the
boundary scan path.
Test Reset. Resets the test state machine.
TRST must be asserted (pulsed low) after
power-up or held low for proper operation of
the ADSP-21020. TRST has a 20 k internal
pullup resistor.
No Connect. No Connects are reserved pins
that must be left open and unconnected.
REV. C