adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 39

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

SDRAM Interface – Bus Master
Use these specifications for ADSP-21161N bus master accesses
of SDRAM:
Table 25. SDRAM Interface
1
2
3
4
5
SDRAM Interface – Bus Slave
These timing requirements allow a bus slave to sample the bus
master’s SDRAM command and detect when a refresh occurs:
Table 26. SDRAM Interface
1
2
3
4
REV. A
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the t
Subtract t
Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE
SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write.
Valid when DSP transitions to SDRAM master from SDRAM slave.
Parameter
Timing Requirements
t
t
t
For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the t
SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency.
Subtract t
Command = SDCKE, RAS, CAS, and SDWE.
SDSDK
HDSDK
DSDK1
SDK
SDKH
SDKL
DCADSDK
HCADSDK
SDTRSDK
SDENSDK
SDCTR
SDCEN
SDSDKTR
SDSDKEN
SDATR
SDAEN
depending upon the SDCKR value and the core clock to CLKIN ratio.
SSDKC1
SCSDK
HCSDK
values, depending upon the SDCKR value and the Core clock to CLKOUT ratio.
CCLK
CCLK
from result if value is greater than or equal to t
from result if value is greater than or equal to t
Data Setup Before SDCLK
Data Hold After SDCLK
First SDCLK Rise Delay After CLKIN
SDCLK Period
SDCLK Width High
SDCLK Width Low
Command, Address, Data, Delay After
SDCLK
Command, Address, Data, Hold After
SDCLK
Data Three-State After SDCLK
Data Enable After SDCLK
Command Three-State After CLKIN
Command Enable After CLKIN
SDCLK Three-State After CLKIN
SDCLK Enable After CLKIN
Address Three-State After CLKIN
Address Enable After CLKIN
First SDCLK Rise
after CLKOUT
Command Setup
before SDCLK
Command Hold
after SDCLK
3
3
–
–
4
Bus Master
Bus Slave
4
1, 2, 3
Min
SDCK
2
1
5
4
CCLK
CCLK
t
CCLK
.
.
1, 2
0.5t
–39–
Min
2.0
2.3
0.75t
t
4
4
2.0
0.75t
0.5t
2
0
1
CCLK
CCLK
0.25 t
0.4
CCLK
CCLK
CCLK
0.5
CCLK
–1.5
+ 1.5
5
Max
SDCKR
Max
0.75t
2
0.25t
0.5t
5
3
4
+7.2
0.5t
0.25t
t
CCLK
t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
ADSP-21161N
0.25t
+ 2.0
+ 6.0
+ 8.0
+2.5
CCLK
DSDK1
DSDK1
+ 2.0
and t
and t
SSDKC1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SSDKC1
Unit
ns
ns
ns
values,