adsp-2165ks-80 Analog Devices, Inc., adsp-2165ks-80 Datasheet - Page 31

• Manufacturer Part Number: adsp-2165ks-80
• Description: Dsp Microcomputers With Rom
• Manufacturer: Analog Devices, Inc.

TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
BUS REQUEST/BUS GRANT
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
NOTES
1
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual, Third Edition, states that, “When BR is recognized, the processor responds immedi-
ately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after BR is recognized.
No external synchronization circuit is needed when BR is generated as an asynchronous signal.
REV. 0
If BR meets the t
BH
BS
SD
SDB
SE
SEC
requires a pulsewidth greater than 10 ns.
BR Hold After CLKOUT High
BR Setup Before CLKOUT Low
CLKOUT High to DMS, PMS,
BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR
Disable to BG Low
BG High to DMS, PMS, BMS,
RD, WR Enable
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
BS
and t
BH
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
PMS, DMS
CLKOUT
CLKOUT
BMS, RD
WR
BG
BR
1
1
Min
29.4
44.4
0
0
14.4
10.24 MHz
t
SD
t
BH
Figure 29. Bus Request/Grant
t
BS
t
Max
44.4
SDB
Min
24.2
39.2
0
0
9.2
13.0 MHz
–31–
Max
39.2
Min
20.0
35.0
0
0
5.0
16.67 MHz
Max
35.0
t
SE
t
SEC
Frequency Dependency
Min
0.25t
0.25t
0
0
0.25t
CK
CK
CK
+ 5
+ 20
– 10
ADSP-216x
Max
0.25t
CK
+ 20
Unit
ns
ns
ns
ns
ns
ns