adsp-21462w Analog Devices, Inc., adsp-21462w Datasheet - Page 14

• Manufacturer Part Number: adsp-21462w
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21462W/ADSP-21465W/ADSP-21467
Table 6. Pin List (Continued)
Name
DDR2_CAS
DDR2_CKE
DDR2_CS
DDR2_DATA
DDR2_DM
DDR2_DQS
DDR2_DQS
DDR2_RAS
DDR2_WE
DDR2_CLK0,
DDR2_CLK0,
DDR2_CLK1,
DDR2_CLK1
DDR2_ODT
AMI_MS
FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
AMI_MS2
FLAG[3]/TIMEX P/
AMI_MS3
LDAT0
LDAT1
LCLK0
LCLK1
LACK0
LACK1
THD_P
THD_M
7–0
7–0
0–1
3-0
1-0
1-0
1-0
15-0
Type
O/T
O/T
O/T
I/O/T
O/T
I/O/T (Differential)
O/T
O/T
O/T (Differential)
O/T
O/T
I/O
I/O
I/O
I/O
I/0
I/O
I/O
I
O
LVTTL SSTL18
Rev. PrA | Page 14 of 60 | November 2008
State
During
and After
Reset
High-Z/
Driven
high
High-Z/
Driven low
High-Z/
Driven
high
High-Z
High-Z/
Driven
high
High-Z
High-Z/
Driven
high
High-Z/
Driven
high
High-Z/
driven low
High-Z/
Driven low
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Description
DDR2 Column Address Strobe. Connect to DDR2_CAS pin, in conjunction
with other DDR2 command pins, defines the operation for the DDR2 to
perform.
DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2
CKE signal.
DDR2 Chip Select. All commands are masked when DDR2_CS
high. DDR2_CS
select the corresponding bank.
DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.
DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled
on both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA
7–0 and DM1 corresponds to DDR2_DATA 15–8.
Data Strobe. Output with Write Data. Input with Read Data. DQS0 corre-
sponds to DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8.
DDR2 Row Address Strobe. Connect to DDR2_RAS pin, in conjunction with
other DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2 Write Enable. Connect to DDR2_WE pin, in conjunction with other
DDR2 command pins, defines the operation for the DDR2 to perform
DDR2 Clock. Free running, minimum frequency not guaranteed during reset.
DDR2 On Die Termination. ODT pin when driven high (along with other
requirements) enables the DDR2 termination resistances.
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for
the corresponding banks of external memory on the AMI interface. The MS
0
other address lines. When no external memory access is occurring the MS
lines are inactive; they are active however when a conditional memory access
instruction is executed, whether or not the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information,
see the ADSP-2146x SHARC Processor Hardware Reference.
FLAG0/Interrupt Request0.
FLAG1/Interrupt Request1.
FLAG2/Interrupt Request2/Async Memory Select2.
FLAG3/Timer Expired/Async Memory Select3.
Link Port Data (Link Ports 0-1).
Link Port Clock (Link Ports 0–1).
Link Port Acknowledge (Link Port 0-1).
Thermal Diode Anode
Thermal Diode Cathode
lines are decoded memory address lines that change at the same time as the
3-0
are decoded emory address lines. Each DDR2_CS
Preliminary Technical Data
3-0
is driven
3-0
lines
1-0
1-